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PCA9616PW,118 PDF预览

PCA9616PW,118

更新时间： 2024-11-14 20:05:39
品牌 Logo 应用领域
恩智浦 - NXP PC光电二极管接口集成电路
页数 文件大小 规格书
32页 951K
描述
PCA9616 - 3-channel multipoint Fast-mode Plus differential I²C-bus buffer with hot-swap logic TSSOP 16-Pin

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PCA9616PW,118 技术参数

是否Rohs认证： 符合生命周期：Active
零件包装代码：TSSOP包装说明：TSSOP-16
针数：16Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：1.61
接口集成电路类型：INTERFACE CIRCUITJESD-30 代码：R-PDSO-G16
长度：5 mm湿度敏感等级：1
功能数量：1端子数量：16
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：NOT SPECIFIED座面最大高度：1.1 mm
最大供电电压：5.5 V最小供电电压：0.8 V
标称供电电压：3.3 V电源电压1-最大：5.5 V
电源电压1-分钟：3 V电源电压1-Nom：5 V
表面贴装：YES温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：4.4 mmBase Number Matches：1

PCA9616PW,118 数据手册

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PCA9616  
3-channel multipoint Fast-mode Plus differential I2C-bus  
buffer with hot-swap logic  
Rev. 2 — 10 March 2014  
Product data sheet  
1. General description  
The PCA9616 is a Fast-mode Plus (Fm+) SMBus/I2C-bus buffer that extends the normal  
single-ended SMBus/I2C-bus through electrically noisy environments using a differential  
SMBus/I2C-bus (dI2C) physical layer, which is transparent to the SMBus/I2C-bus protocol  
layer. It consists of three single-ended to differential driver channels for the SCL (serial  
clock), SDA (serial data), and a third channel useful for INT or other signaling.  
Remark: If the third channel is not used, the INT pin (pin 7 of the TSSOP16 package)  
should not be left disconnected or ‘floating’ (it may generate incorrect bus signals due to  
system noise entering this high-impedance node). Tie it to VSS  
.
The use of differential transmission lines between identical dI2C bus buffers removes  
electrical noise and common-mode offsets that are present when signal lines must pass  
between different voltage domains, are bundled with hostile signals, or run adjacent to  
electrical noise sources, such as high energy power supplies and electric motors.  
The SMBus/I2C-bus was conceived as a simple slow speed digital link for short runs,  
typically on a single PCB or between adjacent PCBs with a common ground connection.  
Applications that extend the bus length or run long cables require careful design to  
preserve noise margin and reject interference.  
The dI2C-bus buffers were designed to solve these problems and are ideally suited for  
rugged high noise environments and/or longer cable applications, allow multiple slaves,  
and operate at bus speeds up to 1 MHz clock rate. Cables can be extended to at least  
three meters (3 m), or longer cable runs at lower clock speeds. The dI2C-bus buffers are  
compatible with existing SMBus/I2C-bus devices and can drive Standard, Fast-mode, and  
Fast-mode Plus devices on the single-ended side.  
Signal direction is automatic, and requires no external control. To prevent bus latch up,  
the standard SMBus/I2C-bus side of the bus buffer, the PCA9616 employs static offset,  
care should be taken when connecting these to other SMBus/I2C-bus buffers that may not  
operate with offset.  
This device is a bridge between the normal 2-wire single-ended wired-OR SMBus/I2C-bus  
and the 4-wire dI2C-bus.  
Additional circuitry allows the PCA9616 to be used for ‘hot swap’ applications, where  
systems are always on, but require insertion or removal of modules or cards without  
disruption to existing signals.  
The PCA9616 has two supply voltages, VDD(A) and VDD(B). VDD(A), the card side supply,  
only serves as a reference and ranges from 0.8 V to 5.5 V. VDD(B), the line side supply,  
serves as the majority supply for circuitry and ranges from 3.0 V to 5.5 V.  
 
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