Datasheet > PCA9618UKZ

PCA9618UKZ

更新时间： 2024-11-12 19:54:47

品牌	Logo	应用领域
恩智浦 - NXP		PC 接口集成电路
页数	文件大小	规格书
22页	966K
描述
PCA9618 - Single channel Fm+ I²C-bus repeater

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PCA9618UKZ 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
包装说明：	,	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.83
接口集成电路类型：	INTERFACE CIRCUIT	湿度敏感等级：	1
峰值回流温度（摄氏度）：	NOT SPECIFIED	处于峰值回流温度下的最长时间：	NOT SPECIFIED
Base Number Matches：	1

PCA9618UKZ 数据手册

PCA9618

Single channel Fm+ I²C-bus repeater

Rev. 1 — 13 January 2016

Product data sheet

1. General description

The PCA9618 is a CMOS integrated circuit that provides Fast-mode Plus (Fm+) I²C-bus

or SMBus buffering of either the SCL or SDA line or can be used in any single bit

applications that require buffering. While retaining all the operating modes and features of

the I²C-bus system, it also permits extension of the I²C-bus by providing bidirectional

buffering, thus enabling buses of 540 pF at 1 MHz or up to 4000 pF at lower speeds.

Using the PCA9618 enables the system designer to isolate two halves of a bus for

capacitance. The DATAA and DATAB pins are overvoltage tolerant and are

high-impedance when the PCA9618 is unpowered.

The PCA9618 can be used to delay the SDA path by at least the minimum propagation

delay, thereby providing an effective data hold time for applications that require an SDA

hold time with respect to SCL. The PCA9618 includes an internal glitch filter, so that it will

ignore glitches rather than expand them, this also means that the minimum propagation

delay is on the order of 46 ns and is reasonably stable over temperature and supply

voltage. Although this is not sufficient to provide the SDA delay requirement of the SMBus

hold time specification of 300 ns, many parts that cannot be used with the 0 ns hold time

of the I²C-bus specification only require a few ns of hold time to work correctly in a

system. For these applications, the PCA9618 is an effective solution.

The PCA9618 can also be used as a buffer on a 1-wire bus similar to how the PCA9617A

is used for the I²C-bus or to buffer the master (microcontroller’s I/O) if the master’s output

is not strong enough to drive the 1-wire bus.

The 2.2 V to 5.5 V bus port B driver has the static level offset, while the port A driver

eliminates the static offset voltage. This results in a LOW on the port B translating into a

nearly 0 V LOW on the port A. This static offset voltage prevents the PCA9618 from

latching into a steady state LOW when driven LOW.

The static offset design of the port B PCA9618 I/O driver prevents it from being connected

to the static or incremented offset sides of other bus buffers. Port A of two or more

PCA9618s can be connected together, also, to allow a star topography with port A on the

common bus. Port A can be connected directly to any other buffer with static or

incremented offset outputs. Multiple PCA9618s can be connected in series, port A to

port B, with no build-up in offset voltage with only time of flight delays to consider.

The output pull-down on the port B internal buffer LOW is set for approximately 0.55 V,

while the input threshold of the internal buffer is set about 90 mV lower (0.45 V). When the

port B I/O is driven LOW internally, the LOW is not recognized as a LOW by the input.

This prevents a latching condition from occurring. The output pull-down on port A drives a

hard LOW and the input level is set at 0.35V_CC

12 3 4 5 6 7...22

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