Datasheet > PCA9541BS/01,118

PCA9541BS/01,118

更新时间： 2024-09-17 15:47:35

品牌	Logo	应用领域
恩智浦 - NXP		PC 外围集成电路
页数	文件大小	规格书
42页	426K
描述
PCA9541 - 2-to-1 I2C-bus master selector with interrupt logic and reset QFN 16-Pin

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PCA9541BS/01,118 技术参数

生命周期：	Obsolete	零件包装代码：	QFN
包装说明：	HVQCCN, LCC16,.16SQ,25	针数：	16
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.61	Is Samacsys：	N
JESD-30 代码：	S-PQCC-N16	JESD-609代码：	e4
长度：	4 mm	湿度敏感等级：	1
端子数量：	16	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	HVQCCN	封装等效代码：	LCC16,.16SQ,25
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	260	电源：	2.5/5 V
认证状态：	Not Qualified	座面最大高度：	1 mm
子类别：	Bus Controllers	最大压摆率：	0.6 mA
最大供电电压：	5.5 V	最小供电电压：	2.3 V
标称供电电压：	2.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)	端子形式：	NO LEAD
端子节距：	0.65 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	4 mm
uPs/uCs/外围集成电路类型：	MICROPROCESSOR CIRCUIT	Base Number Matches：	1

PCA9541BS/01,118 数据手册

PCA9541

2-to-1 I²C-bus master selector with interrupt logic and reset

Rev. 7.1 — 24 June 2015

Product data sheet

1. General description

The PCA9541 is a 2-to-1 I²C-bus master selector designed for high reliability dual master

I²C-bus applications where system operation is required, even when one master fails or

the controller card is removed for maintenance. The two masters (for example, primary

and back-up) are located on separate I²C-buses that connect to the same downstream

I²C-bus slave devices. I²C-bus commands are sent by either I²C-bus master and are used

to select one master at a time. Either master at any time can gain control of the slave

devices if the other master is disabled or removed from the system. The failed master is

isolated from the system and will not affect communication between the on-line master

and the slave devices on the downstream I²C-bus.

Two versions are offered for different architectures. PCA9541/01 with channel 0 selected

at start-up and PCA9541/03 with no channel selected after start-up.

The interrupt outputs are used to provide an indication of which master has control of the

bus. One interrupt input (INT_IN) collects downstream information and propagates it to

the 2 upstream I²C-buses (INT0 and INT1) if enabled. INT0 and INT1 are also used to let

the previous bus master know that it is not in control of the bus anymore and to indicate

the completion of the bus recovery/initialization sequence. Those interrupts can be

disabled and will not generate an interrupt if the masking option is set.

A bus recovery/initialization if enabled sends nine clock pulses, a not acknowledge, and a

STOP condition in order to set the downstream I²C-bus devices to an initialized state

before actually switching the channel to the selected master.

An interrupt is sent to the upstream channel when the recovery/initialization procedure is

completed.

An internal bus sensor senses the downstream I²C-bus traffic and generates an interrupt

if a channel switch occurs during a non-idle bus condition. This function is enabled when

the PCA9541 recovery/initialization is not used. The interrupt signal informs the master

that an external I²C-bus recovery/initialization needs to be performed. It can be disabled

and an interrupt will not be generated.

The pass gates of the switches are constructed such that the V_DDpin can be used to limit

the maximum high voltage, which will be passed by the PCA9541. This allows the use of

different bus voltages on each pair, so that 1.8 V, 2.5 V, or 3.3 V devices can communicate

with 5 V devices without any additional protection.

The PCA9541 does not isolate the capacitive loading on either side of the device, so the

designer must take into account all trace and device capacitances on both sides of the

device, and pull-up resistors must be used on all channels.

External pull-up resistors pull the bus to the desired voltage level for each channel. All I/O

pins are 6.0 V tolerant.

12 3 4 5 6 7...42

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与PCA9541BS/01,118相关器件

型号	品牌	获取价格	描述	数据表
PCA9541BS/02	NXP	获取价格	2-to-1 I2C-bus master selector with interrupt logic and reset
PCA9541BS/03	NXP	获取价格	2-to-1 I2C-bus master selector with interrupt logic and reset
PCA9541D/01	NXP	获取价格	2-to-1 I2C-bus master selector with interrupt logic and reset
PCA9541D/02	NXP	获取价格	2-to-1 I2C-bus master selector with interrupt logic and reset
PCA9541D/03	NXP	获取价格	2-to-1 I2C-bus master selector with interrupt logic and reset
PCA9541PW/01	NXP	获取价格	2-to-1 I2C-bus master selector with interrupt logic and reset
PCA9541PW/02	NXP	获取价格	2-to-1 I2C-bus master selector with interrupt logic and reset
PCA9541PW/03	NXP	获取价格	2-to-1 I2C-bus master selector with interrupt logic and reset
PCA9541PW/03-T	NXP	获取价格	2-to-1 I²C-bus master selector with interrupt logic and reset
PCA9542	NXP	获取价格	2-channel I2C multiplexer and interrupt controller

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