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PCA9510AD PDF预览

PCA9510AD

更新时间： 2024-11-14 21:53:39
品牌 Logo 应用领域
恩智浦 - NXP 接口集成电路光电二极管
页数 文件大小 规格书
23页 137K
描述
Hot swappable I2C-bus and SMBus bus buffer

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中文翻译

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PCA9510AD 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：3.90 MM, PLASTIC, MS-012, SOT96-1, SOP-8针数：8
Reach Compliance Code：compliant风险等级：5.09
Is Samacsys：N接口集成电路类型：INTERFACE CIRCUIT
JESD-30 代码：R-PDSO-G8JESD-609代码：e4
长度：4.9 mm湿度敏感等级：1
功能数量：1端子数量：8
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP8,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
电源：3/5 V认证状态：Not Qualified
座面最大高度：1.75 mm子类别：Other Interface ICs
最大压摆率：6 mA最大供电电压：5.5 V
最小供电电压：2.7 V标称供电电压：3.3 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：NICKEL PALLADIUM GOLD SILVER端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：3.9 mm
Base Number Matches：1

PCA9510AD 数据手册

 浏览型号PCA9510AD的Datasheet PDF文件第2页浏览型号PCA9510AD的Datasheet PDF文件第3页浏览型号PCA9510AD的Datasheet PDF文件第4页浏览型号PCA9510AD的Datasheet PDF文件第5页浏览型号PCA9510AD的Datasheet PDF文件第6页浏览型号PCA9510AD的Datasheet PDF文件第7页 
PCA9510A  
Hot swappable I2C-bus and SMBus bus buffer  
Rev. 01 — 8 September 2005  
Product data sheet  
1. General description  
The PCA9510A is a hot swappable I2C-bus and SMBus buffer that allows I/O card  
insertion into a live backplane without corrupting the data and clock buses. Control  
circuitry prevents the backplane from being connected to the card until a stop command or  
bus idle occurs on the backplane without bus contention on the card. When the  
connection is made, the PCA9510A provides bidirectional buffering, keeping the  
backplane and card capacitances isolated.  
The PCA9510A has no rise time accelerator circuitry to prevent interference when there  
are multiple devices in the same system. The PCA9510A incorporates a digital ENABLE  
input pin, which enables the device when asserted HIGH and forces the device into a Low  
current mode when asserted LOW, and an open-drain READY output pin, which indicates  
that the backplane and card sides are connected together (HIGH) or not (LOW).  
During insertion, the PCA9510A SDAIN and SCLIN pins (inputs only) are precharged to  
1 V to minimize the current required to charge the parasitic capacitance of the chip.  
Remark: The dynamic offset design of the PCA9510A/11A/12A/13A/14A I/O drivers allow  
them to be connected to another PCA9510A/11A/12A/13A/14A device in series or in  
parallel and to the A side of the PCA9517. The PCA9510A/11A/12A/13A/14A cannot  
connect to the static offset I/Os used on the PCA9515/15A/16/16A/18 or PCA9517 B side  
or P82B96 Sx/y side.  
2. Features  
■ Bidirectional buffer for SDA and SCL lines increases fanout and prevents SDA and  
SCL corruption during live board insertion and removal from multi-point backplane  
systems  
■ Compatible with I2C-bus Standard mode, I2C-bus Fast mode, and SMBus standards  
■ Active HIGH ENABLE input  
■ Active HIGH READY open-drain output  
■ High-impedance SDAn and SCLn pins for VCC = 0 V  
■ 1 V precharge on SDAIN and SCLIN inputs  
■ Supports clock stretching and multiple master arbitration and synchronization  
■ Operating power supply voltage range: 2.7 V to 5.5 V  
■ I/Os are not 5.5 V tolerant  
■ 0 Hz to 400 kHz clock frequency  
■ ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per  
JESD22-A115, and 1000 V CDM per JESD22-C101  
■ Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA  
■ Packages offered: SO8, TSSOP8 (MSOP8)  
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