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PCA9511A PDF预览

PCA9511A

更新时间: 2024-02-01 22:21:38
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
23页 141K
描述
Hot swappable I2C-bus and SMBus bus buffer

PCA9511A 技术参数

是否无铅:含铅是否Rohs认证:符合
生命周期:ActiveReach Compliance Code:unknown
风险等级:5.64Is Samacsys:N
Base Number Matches:1

PCA9511A 数据手册

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PCA9511A  
Hot swappable I2C-bus and SMBus bus buffer  
Rev. 01 — 15 August 2005  
Product data sheet  
1. General description  
The PCA9511A is a hot swappable I2C-bus and SMBus buffer that allows I/O card  
insertion into a live backplane without corrupting the data and clock buses. Control  
circuitry prevents the backplane from being connected to the card until a stop command or  
bus idle occurs on the backplane without bus contention on the card. When the  
connection is made, the PCA9511A provides bidirectional buffering, keeping the  
backplane and card capacitances isolated.  
The PCA9511A rise time accelerator circuitry allows the use of weaker DC pull-up  
currents while still meeting rise time requirements. The PCA9511A incorporates a digital  
ENABLE input pin, which enables the device when asserted HIGH and forces the device  
into a low current mode when asserted LOW, and an open-drain READY output pin, which  
indicates that the backplane and card sides are connected together (HIGH) or not (LOW).  
During insertion, the PCA9511A SDA and SCL lines are precharged to 1 V to minimize  
the current required to charge the parasitic capacitance of the chip.  
2. Features  
Bidirectional buffer for SDA and SCL lines increases fan out and prevents SDA and  
SCL corruption during live board insertion and removal from multi-point backplane  
systems  
Compatible with I2C-bus standard mode, I2C-bus fast mode, and SMBus standards  
Built-in V/∆t rise time accelerators on all SDA and SCL lines (0.6 V threshold)  
Active HIGH ENABLE input  
Active HIGH READY open-drain output  
High-impedance SDA and SCL pins for VCC = 0 V  
1 V precharge on all SDA and SCL lines  
Supporting clock stretching and multiple master arbitration/synchronization  
Operating power supply voltage range: 2.7 V to 5.5 V  
0 kHz to 400 kHz clock frequency  
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per  
JESD22-A115, and 1000 V CDM per JESD22-C101  
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA  
Packages offered: SO8, TSSOP8 (MSOP8)  
3. Applications  
cPCI, VME, AdvancedTCA cards and other multi-point backplane cards that are  
required to be inserted or removed from an operating system  

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