Datasheet > PCA9511AD-112

PCA9511AD-112

更新时间： 2024-11-15 12:18:51

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
24页	167K
描述
Hot swappable I2C-bus and SMBus bus buffer Rev. 04 â 19 August 2009

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PCA9511AD-112 数据手册

PCA9511A

Hot swappable I²C-bus and SMBus bus buffer

Rev. 04 — 19 August 2009

Product data sheet

1. General description

The PCA9511A is a hot swappable I²C-bus and SMBus buffer that allows I/O card

insertion into a live backplane without corrupting the data and clock buses. Control

circuitry prevents the backplane from being connected to the card until a stop command or

bus idle occurs on the backplane without bus contention on the card. When the

connection is made, the PCA9511A provides bidirectional buffering, keeping the

backplane and card capacitances isolated.

The PCA9511A rise time accelerator circuitry allows the use of weaker DC pull-up

currents while still meeting rise time requirements. The PCA9511A incorporates a digital

ENABLE input pin, which enables the device when asserted HIGH and forces the device

into a low current mode when asserted LOW, and an open-drain READY output pin, which

indicates that the backplane and card sides are connected together (HIGH) or not (LOW).

During insertion, the PCA9511A SDA and SCL lines are precharged to 1 V to minimize

the current required to charge the parasitic capacitance of the chip.

2. Features

I Bidirectional buffer for SDA and SCL lines increases fan out and prevents SDA and

SCL corruption during live board insertion and removal from multipoint backplane

systems

I Compatible with I²C-bus Standard-mode, I²C-bus Fast-mode, and SMBus standards

I Built-in ∆V/∆t rise time accelerators on all SDA and SCL lines (0.6 V threshold)

requires the bus pull-up voltage and supply voltage (V_CC) to be the same

I Active HIGH ENABLE input

I Active HIGH READY open-drain output

I High-impedance SDA and SCL pins for V_CC= 0 V

I 1 V precharge on all SDA and SCL lines

I Supporting clock stretching and multiple master arbitration/synchronization

I Operating power supply voltage range: 2.7 V to 5.5 V

I 0 Hz to 400 kHz clock frequency

I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per

JESD22-A115, and 1000 V CDM per JESD22-C101

I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

I Packages offered: SO8, TSSOP8 (MSOP8)

12 3 4 5 6 7...24

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