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PCA9512BD PDF预览

PCA9512BD

更新时间: 2024-11-15 12:48:31
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
27页 320K
描述
Level shifting hot swappable I2C-bus and SMBus bus buffer

PCA9512BD 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:3.90 MM, PLASTIC, MS-012, SOT96-1, SOP-8
针数:8Reach Compliance Code:unknown
风险等级:5.58接口集成电路类型:INTERFACE CIRCUIT
JESD-30 代码:R-PDSO-G8JESD-609代码:e4
长度:4.9 mm湿度敏感等级:1
功能数量:1端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1.75 mm最大供电电压:5.5 V
最小供电电压:2.7 V标称供电电压:3.3 V
电源电压1-最大:5.5 V电源电压1-分钟:2.7 V
电源电压1-Nom:3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.9 mmBase Number Matches:1

PCA9512BD 数据手册

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PCA9512A; PCA9512B  
Level shifting hot swappable I2C-bus and SMBus bus buffer  
Rev. 6 — 1 March 2013  
Product data sheet  
1. General description  
The PCA9512A/B is a hot swappable I2C-bus and SMBus buffer that allows I/O card  
insertion into a live backplane without corruption of the data and clock buses and includes  
two dedicated supply voltage pins to provide level shifting between 3.3 V and 5 V systems  
while maintaining the best noise margin for each voltage level. Either pin may be powered  
with supply voltages ranging from 2.7 V to 5.5 V with no constraints on which supply  
voltage is higher. Control circuitry prevents the backplane from being connected to the  
card until a stop bit or bus idle occurs on the backplane without bus contention on the  
card. When the connection is made, the PCA9512A/B provides bidirectional buffering,  
keeping the backplane and card capacitances isolated.  
Both the PCA9512A and PCA9512B use identical silicon (PCN201012007F dated  
13 Dec 2010), so the PCA9512B will be discontinued in the near future and is not  
recommended for new designs.  
The PCA9512A/B rise time accelerator circuitry allows the use of weaker DC pull-up  
currents while still meeting rise time requirements. The PCA9512A/B incorporates a digital  
input pin that enables and disables the rise time accelerators on all four SDAn and SCLn  
pins.  
During insertion, the PCA9512A/B SDAn and SCLn pins are precharged to 1 V to  
minimize the current required to charge the parasitic capacitance of the chip.  
The incremental offset design of the PCA9510A/11A/12A/12B/13A/14A I/O drivers allows  
them to be connected to another PCA9510A/11A/12A/12B/13A/14A device in series or in  
parallel and to the I2C compliant side of static offset bus buffers, but not to the static offset  
side of those bus buffers.  
2. Features and benefits  
Bidirectional buffer for SDA and SCL lines increases fan-out and prevents SDA and  
SCL corruption during live board insertion and removal from multipoint backplane  
systems  
Compatible with I2C-bus Standard mode, I2C-bus Fast mode, and SMBus standards  
Built-in V/t rise time accelerators on all SDA and SCL lines (0.6 V threshold) with  
ability to disable V/t rise time accelerator through the ACC pin for lightly loaded  
systems, requires the bus pull-up voltage and respective supply voltage (VCC or VCC2  
to be the same  
)
5 V to 3.3 V level translation with optimum noise margin  
High-impedance SDAn and SCLn pins for VCC or VCC2 = 0 V  
1 V precharge on all SDAn and SCLn pins  
Supports clock stretching and multiple master arbitration and synchronization  

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