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PCA9511ADR2G PDF预览

PCA9511ADR2G

更新时间： 2024-11-15 12:48:11
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
17页 352K
描述
Hot Swappable I2C-Bus and SMBus Bus Buffer

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中文翻译

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PCA9511ADR2G 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：SOP,Reach Compliance Code：compliant
风险等级：5.6接口集成电路类型：INTERFACE CIRCUIT
JESD-30 代码：R-PDSO-G8JESD-609代码：e3
长度：4.9 mm湿度敏感等级：1
功能数量：1端子数量：8
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
座面最大高度：1.75 mm最大供电电压：5.5 V
最小供电电压：2.7 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：Tin (Sn)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL宽度：3.9 mm
Base Number Matches：1

PCA9511ADR2G 数据手册

 浏览型号PCA9511ADR2G的Datasheet PDF文件第2页浏览型号PCA9511ADR2G的Datasheet PDF文件第3页浏览型号PCA9511ADR2G的Datasheet PDF文件第4页浏览型号PCA9511ADR2G的Datasheet PDF文件第5页浏览型号PCA9511ADR2G的Datasheet PDF文件第6页浏览型号PCA9511ADR2G的Datasheet PDF文件第7页 
PCA9511A  
Hot Swappable I2C-Bus and  
SMBus Bus Buffer  
2
The PCA9511A is a hot swappable I C−bus and SMBus buffer that  
allows I/O card insertion into a live backplane without corrupting the  
data and clock buses. Control circuitry prevents the backplane from  
being connected to the card until a stop command or bus idle occurs on  
the backplane without bus contention on the card. When the  
connection is made, the PCA9511A provides bidirectional buffering,  
keeping the backplane and card capacitances isolated.  
http://onsemi.com  
MARKING  
DIAGRAMS  
The PCA9511A rise time accelerator circuitry allows the use of  
weaker DC pull−up currents while still meeting rise time  
requirements. The PCA9511A incorporates a digital ENABLE input  
pin, which enables the device when asserted HIGH and forces the  
device into a low current mode when asserted LOW, and an  
open−drain READY output pin, which indicates that the backplane  
and card sides are connected together (HIGH) or not (LOW).  
During insertion, the PCA9511A SDA and SCL lines are  
precharged to 1 V to minimize the current required to charge the  
parasitic capacitance of the chip.  
8
Micro8]  
DM SUFFIX  
CASE 846A  
9511  
AYWG  
G
1
8
9511  
AYWW  
SOIC−8  
CASE 751  
8
1
G
1
Features  
A
L
M
Y
W
G
= Assembly Location  
= Wafer Lot  
= Date Code  
= Year  
= Work Week  
= Pb−Free Package  
• Bidirectional Buffer for SDA and SCL Lines Increases Fan−Out and  
Prevents SDA and SCL Corruption During Live Board Insertion and  
Removal from Multipoint Backplane Systems  
• DV/Dt Rise Time Accelerators on all SDA and SCL lines  
• Active HIGH ENABLE Input  
• Active HIGH READY Open−Drain Output  
• High−Impedance SDA and SCL for V = 0 V  
(Note: Microdot may be in either location)  
ORDERING INFORMATION  
See detailed ordering and shipping information on page 15 of  
this data sheet.  
CC  
• 1 V precharge on all SDA and SCL Lines  
• Supports Clock Stretching and Multiple Master  
arbitration/Synchronization  
• V Operating Range: 2.7 V to 5.5 V  
CC  
2
• I C and SMBus SCL Clock Frequency up to 1 MHz  
• Alternate Features for  
PCA9510A/PCA9512A/PCA9513A/PCA9514A  
• Available in: Micro8, SOIC−8  
• ESD Performance: 8000 V HBM, 600 V MM, 2000V CDM  
• These are Pb−Free Devices  
Applications  
• cPCI, VME, AdvancedTCA cards and other multipoint backplane  
cards that are required to be inserted or removed from an operating  
system  
© Semiconductor Components Industries, LLC, 2013  
1
Publication Order Number:  
August, 2013 − Rev. 0  
PCA9511A/D  
1234567...17

中文翻译

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