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PCA9512AD

更新时间： 2024-01-10 03:41:58

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
23页	145K
描述
Level shifting hot swappable I2C-bus and SMBus bus buffer

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技术参数
数据手册

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PCA9512AD 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	SOIC	包装说明：	TSSOP, TSSOP8,.19
针数：	8	Reach Compliance Code：	unknown
风险等级：	5.81	接口集成电路类型：	INTERFACE CIRCUIT
JESD-30 代码：	S-PDSO-G8	长度：	3 mm
湿度敏感等级：	1	功能数量：	1
端子数量：	8	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装等效代码：	TSSOP8,.19
封装形状：	SQUARE	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	3/5 V
认证状态：	Not Qualified	座面最大高度：	1.1 mm
子类别：	Other Interface ICs	最大压摆率：	3.6 mA
最大供电电压：	5.5 V	最小供电电压：	2.7 V
标称供电电压：	3.3 V	表面贴装：	YES
温度等级：	INDUSTRIAL	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	3 mm

PCA9512AD 数据手册

PCA9512A

Level shifting hot swappable I²C-bus and SMBus bus buffer

Rev. 04 — 19 August 2009

Product data sheet

1. General description

The PCA9512A is a hot swappable I²C-bus and SMBus buffer that allows I/O card

insertion into a live backplane without corruption of the data and clock buses and includes

two dedicated supply voltage pins to provide level shifting between 3.3 V and 5 V systems

while maintaining the best noise margin for each voltage level. Either pin may be powered

with supply voltages ranging from 2.7 V to 5.5 V with no constraints on which supply

voltage is higher. Control circuitry prevents the backplane from being connected to the

card until a stop bit or bus idle occurs on the backplane without bus contention on the

card. When the connection is made, the PCA9512A provides bidirectional buffering,

keeping the backplane and card capacitances isolated.

The PCA9512A rise time accelerator circuitry allows the use of weaker DC pull-up

currents while still meeting rise time requirements. The PCA9512A incorporates a digital

input pin that enables and disables the rise time accelerators on all four SDAn and SCLn

pins.

During insertion, the PCA9512A SDAn and SCLn pins are precharged to 1 V to minimize

the current required to charge the parasitic capacitance of the chip.

The dynamic offset design of the PCA9510A/11A/12A/13A/14A I/O drivers allow them to

be connected to another PCA9510A/11A/12A/13A/14A device in series or in parallel and

to the A side of the PCA9517. The PCA9510A/11A/12A/13A/14A cannot connect to the

static offset I/Os used on the PCA9515/15A/16/16A/18, PCA9517 B side, or

P82B96 Sx/y side.

2. Features

I Bidirectional buffer for SDA and SCL lines increases fan-out and prevents SDA and

SCL corruption during live board insertion and removal from multipoint backplane

systems

I Compatible with I²C-bus Standard mode, I²C-bus Fast mode, and SMBus standards

I Built-in ∆V/∆t rise time accelerators on all SDA and SCL lines (0.6 V threshold) with

ability to disable ∆V/∆t rise time accelerator through the ACC pin for lightly loaded

systems, requires the bus pull-up voltage and respective supply voltage (V_CCor V_CC2

)

to be the same

I 5 V to 3.3 V level translation with optimum noise margin

I High-impedance SDAn and SCLn pins for V_CCor V_CC2= 0 V

I 1 V precharge on all SDAn and SCLn pins

I Supports clock stretching and multiple master arbitration and synchronization

I Operating power supply voltage range: 2.7 V to 5.5 V

I 0 Hz to 400 kHz clock frequency

12 3 4 5 6 7...23

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与PCA9512AD相关器件

型号	品牌	获取价格	描述	数据表
PCA9512ADP	NXP	获取价格	Level shifting hot swappable I2C-bus and SMBus bus buffer
PCA9512ADP,112	NXP	获取价格	Interface Circuit, PDSO8
PCA9512B	NXP	获取价格	Smart, simple solutions for the 12 most common design concerns
PCA9512BD	NXP	获取价格	Level shifting hot swappable I2C-bus and SMBus bus buffer
PCA9512BD,118	NXP	获取价格	PCA9512A; PCA9512B - Level shifting hot swapp
PCA9512BDP	NXP	获取价格	Level shifting hot swappable I2C-bus and SMBus bus buffer
PCA9512D	NXP	获取价格	Level shifting hot swappable I2C and SMBus buffer
PCA9512D,112	NXP	获取价格	PCA9512D
PCA9512DP	NXP	获取价格	Level shifting hot swappable I2C and SMBus buffer
PCA9512DP,118	NXP	获取价格	PCA9512DP

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