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PCA9508DP PDF预览

PCA9508DP

更新时间： 2024-11-15 12:19:47
品牌 Logo 应用领域
恩智浦 - NXP 驱动程序和接口接口集成电路中继器光电二极管
页数 文件大小 规格书
21页 135K
描述
Hot swappable level translating I2C-bus repeater

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中文翻译

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PCA9508DP 技术参数

是否Rohs认证： 符合生命周期：Active
零件包装代码：SOIC包装说明：3 MM, PLASTIC, SOT505-1, TSSOP-8
针数：8Reach Compliance Code：compliant
风险等级：5.09Is Samacsys：N
接口集成电路类型：INTERFACE CIRCUITJESD-30 代码：S-PDSO-G8
JESD-609代码：e4长度：3 mm
湿度敏感等级：1功能数量：1
端子数量：8最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP8,.19
封装形状：SQUARE封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260电源：3/5 V
认证状态：Not Qualified座面最大高度：1.1 mm
子类别：Line Driver or Receivers最大供电电压：5.5 V
最小供电电压：0.9 V标称供电电压：2.7 V
电源电压1-最大：5.5 V电源电压1-分钟：2.7 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：NICKEL PALLADIUM GOLD
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：3 mmBase Number Matches：1

PCA9508DP 数据手册

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PCA9508  
Hot swappable level translating I2C-bus repeater  
Rev. 01 — 28 April 2008  
Product data sheet  
1. General description  
The PCA9508 is a CMOS integrated circuit that supports hot-swap with zero offset and  
provides level shifting between low voltage (down to 0.9 V) and higher voltage (2.7 V to  
5.5 V) for I2C-bus or SMBus applications. While retaining all the operating modes and  
features of the I2C-bus system during the level shifts, it also permits extension of the  
I2C-bus by providing bidirectional buffering for both the data (SDA) and the clock (SCL)  
lines, thus enabling two buses of 400 pF. Using the PCA9508 enables the system  
designer to isolate two halves of a bus for both voltage and capacitance, and perform  
hot-swap and voltage level translation. Furthermore, the dual supply pins can be powered  
up in any sequence; when any of the supply pins are unpowered, the 5 V tolerant I/O are  
high-impedance.  
The hot swap feature allows an I/O card to be inserted into a live backplane without  
corrupting the data and clock buses. Control circuitry prevents the backplane from being  
connected to the card until a stop command or bus idle occurs on the backplane without  
bus contention on the card. Zero offset output voltage allows multiple PCA9508s to be put  
in series and still maintains an excellent noise margin.  
PCA9508 has B side and A side bus drivers. The 2.7 V to 5.5 V bus B side drivers behave  
much like the drivers on the PCA9515A device, while the adjustable voltage bus A side  
drivers drive more current and incur no static offset voltage. This results in a LOW on the  
B side translating into a nearly 0 V LOW on the A side.  
The static offset design of the B side PCA9508 I/O drivers prevents them from being  
connected to another device that has a rise time accelerator including the PCA9510/A,  
PCA9511/A, PCA9512/A, PCA9513/A, or PCA9514/A or a static offset voltage including  
the PCA9507 (B side), PCA9508 (B side), PCA9509 (A side), PCA9515/A, PCA9516A,  
PCA9517/A (B side), PCA9518, PCA9519 (A side), or P82B96/PCA9600 (Sx/Sy side).  
The A side of two or more PCA9508s can be connected together, however, to allow a star  
topology with the A side on the common bus, and the A side can be connected directly to  
any other buffer with static or dynamic offset voltage. Multiple PCA9508s can be  
connected in series, A side to B side, with no build-up in offset voltage with only  
time-of-flight delays to consider.  
The PCA9508 drivers are not enabled unless the bus is idle, VCC(A) is above 0.8 V and  
VCC(B) is above 2.5 V. The EN pin can also be used to turn the drivers on and off under  
system control. Caution should be observed to only change the state of the enable pin  
when the bus is idle.  
The output pull-down on the B side internal buffer LOW is set for approximately 0.5 V,  
while the input threshold of the internal buffer is set about 70 mV lower (0.43 V). When the  
B side I/O is driven LOW internally, the LOW is not recognized as a LOW by the input.  
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