Datasheet > P4C1024-35C6MB

P4C1024-35C6MB

更新时间： 2023-08-15 00:00:00

品牌	Logo	应用领域
PYRAMID		静态存储器
页数	文件大小	规格书
14页	923K
描述
Standard SRAM, 128KX8, 35ns, CMOS, CDIP32, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-32

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P4C1024-35C6MB 数据手册

P4C1024

POWER DISSIPATION CHARACTERISTICS VS. SPEED

Temperature

Range

Symbol

Parameter

-15 -20 -25 -35 -45 -55 -70 -85 -100 -120 Unit

Commercial

190 160 150 145 N/A N/A N/A N/A N/A N/A mA

N/A 175 165 160 155 N/A N/A N/A N/A N/A mA

N/A 150 140 135 130 125 115 110 105 100 mA

Dynamic

Operating

Current*

I_CC

Industrial

Military

*V_CC= 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE₁= V_IL, CE₂= V_IH, OE = V_IH

DATA RETENTION CHARACTERISTICS (P4C1024L, Military Temperature Only)

Typ.*

V_CC=

2.0V

Max

V_CC=

2.0V

Symbol

Parameter

Test Condition

Min

Unit

3.0V

V_DR

V_CCfor Data Retention

Data Retention Current

2.0

I_CCDR

200

400

600

µA

CE₁≥ V_CC– 0.2V or

CE₂≤ 0.2V, V_IN≥ V_CC– 0.2V

or V_IN≤ 0.2V

t_CDR

Chip Deselect to

Data Retention Time

Operation Recovery Time

†

t_R

t_RC

*T_A= +25°C

t_RC= Read Cycle Time

†

This parameter is guaranteed but not tested.

DATA RETENTION WAVEFORM

Document # SRAM124 REV C

Page 3 of 14

1 234 5 6 7...14

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