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NTE4027BT

更新时间： 2024-11-03 21:15:31

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NTE4027BT 技术参数

NTE4027B & NTE4027BT

Integrated Circuit

CMOS, Dual J−K Flip−Flop

Description:

The NTE4027B (16−Lead DIP) and NTE4027BT (SOIC−16) dual J−K flip−flops have independent J,

K, Clock (C), Set (S) and Reset (R) inputs for each flip−flop. These devices may be used in control,

Features:

D Diode Protection on All Inputs

D Supply Voltage Range: 3Vdc to 18Vdc

D Logic Swing Independent of Fanout

D Logic Edge−Clocked Flip−Flop Design —

Logic State is retained Indefinitely with Clock Level either High or Low; Information is Transferred

to the Output Only on the Positive−Going Edge o the Clock Pulse

D Capable of Driving Two Low−Power TTL Loads or One Low−Power Schottky TTL Load Over

the Rated Temperature Range

Absolute Maximum Ratings: (Voltages referenced to V_SS, Note 1)

DC Supply Voltage, V_DD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to +18.0V

Input Voltage (DC or Transient), V_in. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to V_DDto +0.5V

Output Voltage (DC or Transient), V_out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to V_DDto +0.5V

Input Current (DC or Transient, Per Pin), I_in. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA

Output Current (DC or Transient, Per Pin), I_out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA

Power Dissipation (Per Package), P_D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mW

Temperature Derating (from +65° to +125°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −7.0mW/°C

Storage Temperature, T_stg. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65° to +150°C

Lead Temperature (During Soldering, 8sec max), T_L. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +260°C

Note 1. Maximum Ratings are those values beyond which damage to the device may occur.

12 3 4 5

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