NTE4047B and NTE4047BT
Integrated Circuit
CMOS, Low−Power Monostable/Astable Multivibrator
Description:
The NTE4047B (14−Lead DIP) and NTE4047BT (SOIC−14) consists of a gatable astable multivi-
brator with logic techniques incorporated to permit a positive or negative edge−triggered mono-
stable multivibrator action with retriggering and external counting options.
Inputs include (+) TRIGGER, (−) TRIGGER, ASTABLE, ASTABLE, RETRIGGER, and EXTERNAL
RESET. Buffered outputs are Q, Q, and OSCILLATOR. In all modes of operation, an external capa-
citor must be connected between C−Timing and R−C Common terminals, and an external resistor
must be connected between the R−Timing and R−C Common terminals.
Astable operation is enabled by a high level on the ASTABLE input of a low level on the ASTABLE
input, or both. The period of the square wave at the Q and Q outputs in this mode of operation i a
function of the external components employed. “True” input pulses on the ASTABLE input or “Com-
plement” pulses on the ASTABLE input allow the circuit to be used as a gatable multivibrator. The
OSCILLATOR output period will be half of the Q teminal output in the astable mode. However, a 50%
duty cycle is not guaranteed at this output.
The NTE4047B/BT triggers in the monostable mode when a positive−going edge occurs on the (+)
TRIGGER input while the (−) TRIGGER is held low. Input pulses may be of any duration relative
to the output pulse.
If retrigger capability is desired, the RETRIGGER input is pulsed. The retriggerable mode of opera-
tion is limited to positive−going edge. The NTE4047B/BT will retrigger as long as the RETRIGGER
input is high, with or without transitions.
An external countdown option can be implemented by coupling “Q” to an external “N” counter and
resetting the counter with the trigger pulse. The counter output pulse is fed back to the ASTABLE
input and has a duration equal to N times the period of the multivibrator.
A high level on the EXTERNAL RESET input assures no output pulse during an “ON” power condi-
tion. This input can also be activated to terminate the output pulse at any time. For monostable oper-
ation, whenever VDD is applied, an internal power−on reset circuit will clock the Q output low within
one output period (tM).
Features:
D Very Low Power Consumption: Special CMOS Oscillator Configuration
D Monostable (One−Shot) or Astable (Free−Running) Operation
D True and Complemented Buffered Outputs
D Buffered Inputs
D Standardized, Symmetrical Output Characteristics
D 5V, 10V, and 15V Parametric Ratings