Datasheet > NTE4042BT

NTE4042BT

更新时间： 2024-11-03 20:09:31

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NTE4042BT 技术参数

NTE4042B & NTE4042BT

Integrated Circuit

CMOS, Quad Transparent Latch

Description:

The NTE4042B (16−Lead DIP) and NTE4042BT (SOIC−16) are quad transparent latch devices

constructed with MOS P−Channel and N−Channel enhancement mode devices in a single mono-

lithic structure. Each latch has a separate data input, but all four latches share a common clock. The

clock polarity (high or low) used to strobe data through the latches can be reversed using the polarity

input. Information present at the data input is transferred to outputs Q and Q during the clock level

which is determined by the polarity input. When the polarity input is in the logic “0” state, data is

transferred during the low clock level, and when the polarity input is in the logic “1” state the transfer

occurs during the high clock level.

Features:

D Buffered Data Inputs

D Common Clock

D Clock Polarity Control

D Q and Q Outputs

D Double Diode Input Protection

D Supply Voltage Range: 3Vdc to 18Vdc

D Capable of Driving Two Low−Power TTL Loads or One Low−Power Schottky TTL Load Over

the Rated Temperature Range

Absolute Maximum Ratings: (Voltages referenced to V_SS, Note 1)

DC Supply Voltage, V_DD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to +18.0V

Input Voltage (DC or Transient), V_in. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to V_DDto +0.5V

Output Voltage (DC or Transient), V_out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to V_DDto +0.5V

Input Current (DC or Transient, Per Pin), I_in. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA

Output Current (DC or Transient, Per Pin), I_out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA

Power Dissipation (Per Package), P_D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mW

Temperature Derating (from +65° to +125°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −7.0mW/°C

Storage Temperature Range, T_stg. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65° to +150°C

Lead Temperature (During Soldering, 8sec max), T_L. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +260°C

Note 1. Maximum Ratings are those values beyond which damage to the device may occur.

12 3 4 5

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