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NT6AP512T32AV-J2 PDF预览

NT6AP512T32AV-J2

更新时间: 2024-09-19 02:45:23
品牌 Logo 应用领域
南亚科技 - NANYA 动态存储器双倍数据速率光电二极管
页数 文件大小 规格书
328页 11988K
描述
Commercial Mobile LPDDR4 X 8 Gb/ 16 Gb DDP)/32Gb(QDP) SDRAM

NT6AP512T32AV-J2 技术参数

是否Rohs认证: 符合生命周期:Active
Reach Compliance Code:compliant风险等级:5.72
Base Number Matches:1

NT6AP512T32AV-J2 数据手册

 浏览型号NT6AP512T32AV-J2的Datasheet PDF文件第2页浏览型号NT6AP512T32AV-J2的Datasheet PDF文件第3页浏览型号NT6AP512T32AV-J2的Datasheet PDF文件第4页浏览型号NT6AP512T32AV-J2的Datasheet PDF文件第5页浏览型号NT6AP512T32AV-J2的Datasheet PDF文件第6页浏览型号NT6AP512T32AV-J2的Datasheet PDF文件第7页 
NTC Proprietary  
Level: Property  
Preliminary, Subject to change  
LPDDR4X 8Gb/16Gb(DDP)/32Gb(QDP) SDRAM  
8Gb: NT6AP512M16AV/16Gb: NT6AP512T32AV  
32Gb: NT6AP1024F32AV  
Commercial Mobile LPDDR4X 8Gb/16Gb(DDP)/32Gb(QDP) SDRAM  
Features  
Data Integrity  
Basis LPDDR4X Compliant  
- Low Power Consumption  
- DRAM built-in Temperature Sensor for  
Temperature Compensated Self Refresh (TCSR)  
- 16n Prefetch Architecture and BL16, BL32 (OTF)  
- Auto Refresh and Self Refresh Modes  
Power Saving Modes  
Signal Integrity  
- Internal VREF and VREF Training  
- Configurable DS for system compatibility  
- Configurable On-Die Termination  
- Partial Array Self Refresh (PASR)  
- Frequency Set Point(WR/OP)  
- ZQ Calibration for DS/ODT impedance accuracy via  
external ZQ pad (240Ω± 1%)  
- Clock-stop capability  
LVSTL interface and Power Supply  
- VDD1/VDD2/VDDQ = 1.8V/1.1V/0.6V  
- Data bus inversion (DBI)  
Training for SignalsSynchronization  
- DQ Calibration offering specific DQ output patterns  
Programmable  
RL/WL Select (Set A / Set B)  
nWR (X16 mode / X8 Byte mode)  
PASR (bank/segment)  
RON (Typical:40/48/60/80/120/240)  
RTT (40/48/60/80/120/240)  
Options  
Speed Grade (DataRate)  
Temperature Range (Tc)  
- Commercial Grade : - 30to +85, extending 1052  
-4267 Mbps / RL=36  
-3733 Mbps / RL=32  
-3200 Mbps / RL=28  
Package Information  
Density and Addressing  
Lead-free RoHS compliance and Halogen-free  
Items  
Width x Length x Height  
(mm)  
Ball pitch  
(mm)  
Items  
X16_1CH X16_2CH X16_2CH  
(FBGA Package)  
Die Quantity  
Number of Banks  
Bank Address  
Row  
Single Die Dual Die  
Quad Die  
8
0.65/0.80  
Mixed  
8
8
200 Ball  
(SDP/DDP)  
10.00 x 15.00 x 0.83  
10.00 x 15.00 x 1.05  
BA[2:0]  
R[15:0]  
C[9:0]  
BA[2:0]  
R[15:0]  
C[9:0]  
3.9μs  
BA[2:0]  
R[15:0]  
C[9:0]  
Column  
0.65/0.80  
Mixed  
Tc85  
200 Ball  
(QDP)  
tREFI 1 85<Tc95℃  
95<Tc105℃  
1.95μs  
0.975μs  
Notes:  
1.  
2.  
tREFI values for all bank refresh is within temperature specification (<= 85)  
AC/DC will be derated when above 85.  
1
Version 1.2  
Nanya Technology Corp.  
NTC has the rights to change any specifications or product without notification.  
09/2018  
All Rights Reserved ©  

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