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NSBC144EDXV6T5 PDF预览

NSBC144EDXV6T5

更新时间: 2024-01-21 08:20:50
品牌 Logo 应用领域
安森美 - ONSEMI 开关光电二极管晶体管
页数 文件大小 规格书
10页 93K
描述
100mA, 50V, 2 CHANNEL, NPN, Si, SMALL SIGNAL TRANSISTOR, LEAD FREE, PLASTIC, CASE 463A-01, 6 PIN

NSBC144EDXV6T5 技术参数

是否无铅: 不含铅生命周期:Active
包装说明:SMALL OUTLINE, R-PDSO-F6针数:6
Reach Compliance Code:compliantECCN代码:EAR99
Factory Lead Time:1 week风险等级:5.37
其他特性:BUILT IN BIAS RESISTOR RATIO IS 1最大集电极电流 (IC):0.1 A
集电极-发射极最大电压:50 V配置:SEPARATE, 2 ELEMENTS WITH BUILT-IN RESISTOR
最小直流电流增益 (hFE):80JESD-30 代码:R-PDSO-F6
JESD-609代码:e3湿度敏感等级:1
元件数量:2端子数量:6
最高工作温度:150 °C封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260极性/信道类型:NPN
最大功率耗散 (Abs):0.5 W认证状态:Not Qualified
子类别:BIP General Purpose Small Signal表面贴装:YES
端子面层:Tin (Sn)端子形式:FLAT
端子位置:DUAL处于峰值回流温度下的最长时间:40
晶体管应用:SWITCHING晶体管元件材料:SILICON
Base Number Matches:1

NSBC144EDXV6T5 数据手册

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NSBC114EDXV6T1,  
NSBC114EDXV6T5  
Preferred Devices  
Dual Bias Resistor  
Transistors  
NPN Silicon Surface Mount Transistors  
with Monolithic Bias Resistor Network  
http://onsemi.com  
(3)  
(2)  
(1)  
The BRT (Bias Resistor Transistor) contains a single transistor with  
a monolithic bias network consisting of two resistors; a series base  
resistor and a base−emitter resistor. These digital transistors are  
designed to replace a single device and its external resistor bias  
network. The BRT eliminates these individual components by  
integrating them into a single device. In the NSBC114EDXV6T1  
series, two BRT devices are housed in the SOT−563 package which is  
ideal for low power surface mount applications where board space is at  
a premium.  
R
R
1
2
Q
1
Q
2
R
2
R
1
(4)  
(5)  
(6)  
NSBC114EDXV6T1  
Simplifies Circuit Design  
Reduces Board Space  
Reduces Component Count  
Lead−Free Solder Plating  
4
5
6
3
2
1
MAXIMUM RATINGS  
(T = 25°C unless otherwise noted, common for Q and Q )  
A
SOT−563  
CASE 463A  
PLASTIC  
1
2
Rating  
Symbol  
Value  
Unit  
Vdc  
Collector-Base Voltage  
Collector-Emitter Voltage  
Collector Current  
V
50  
50  
CBO  
CEO  
V
Vdc  
MARKING DIAGRAM  
I
C
100  
mAdc  
THERMAL CHARACTERISTICS  
xx D  
Characteristic  
(One Junction Heated)  
Symbol  
Max  
Unit  
xx = Specific Device Code  
Total Device Dissipation  
P
D
(see table on following page)  
= Date Code  
T = 25°C  
Derate above 25°C  
357 (Note 1)  
2.9 (Note 1)  
mW  
mW/°C  
A
D
Thermal Resistance −  
Junction-to-Ambient  
R
350 (Note 1)  
°C/W  
q
JA  
ORDERING INFORMATION  
Characteristic  
Device  
Package  
Shipping  
(Both Junctions Heated)  
Symbol  
Max  
Unit  
NSBC114EDXV6T1 SOT−563  
4 mm pitch  
4000/Tape & Reel  
Total Device Dissipation  
P
D
T = 25°C  
500 (Note 1)  
4.0 (Note 1)  
mW  
mW/°C  
A
NSBC114EDXV6T5 SOT−563  
2 mm pitch  
Derate above 25°C  
8000/Tape & Reel  
Thermal Resistance −  
Junction-to-Ambient  
R
250 (Note 1)  
°C/W  
°C  
q
JA  
DEVICE MARKING INFORMATION  
Junction and Storage  
Temperature Range  
T , T  
J stg  
55 to +150  
See specific marking information in the device marking table  
on page 2 of this data sheet.  
1. FR−4 @ Minimum Pad  
Preferred devices are recommended choices for future use  
and best overall value.  
Semiconductor Components Industries, LLC, 2004  
1
Publication Order Number:  
January, 2004 − Rev. 4  
NSBC114EDXV6/D  
 

NSBC144EDXV6T5 替代型号

型号 品牌 替代类型 描述 数据表
NSBC144EDXV6T5G ONSEMI

完全替代

Dual NPN Bias Resistor Transistors R1 = 47 K , R2 = 47 K
NSBC144EDXV6T1G ONSEMI

完全替代

Dual NPN Bias Resistor Transistors R1 = 47 K , R2 = 47 K
NSBC144EDXV6T1 ONSEMI

完全替代

Dual Bias Resistor Transistors

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