NS16C2552, NS16C2752
www.ti.com
SNLS238D –AUGUST 2006–REVISED APRIL 2013
NS16C2552/NS16C2752 Dual UART with 16-byte/64-byte FIFO's and up to 5 Mbit/s Data
Rate
Check for Samples: NS16C2552, NS16C2752
1
FEATURES
•
•
Multi-Function Output Allows More Package
Functions with Fewer I/O Pins
2
•
Dual Independent UART
44-PLCC or 48-TQFP Package
•
•
•
Up to 5 Mbits/s Data Transfer Rate
2.97 V to 5.50 V Operational Vcc
DESCRIPTION
The NS16C2552 and NS16C2752 are dual channel
Universal
5 V Tolerant I/Os in the Entire Supply Voltage
Range
Asynchronous
Receiver/Transmitter
•
•
Industrial Temperature: -40°C to 85°C
(DUART). The footprint and the functions are
compatible to the PC16552D, while new features are
added to the UART device. These features include
low voltage support, 5V tolerant inputs, enhanced
features, enhanced register set, and higher data rate.
Default Registers are Identical to the
PC16552D
•
NS16C2552/NS16C2752 is Pin-to-Pin
Compatible to TI PC16552D, EXAR ST16C2552,
XR16C2552, XR 16L2552, and Phillips
SC16C2552B
The two serial channels are completely independent
of each other, except for a common CPU interface
and crystal input. On power-up both channels are
functionally identical to the PC16552D. Each channel
can operate with on-chip transmitter and receiver
FIFO’s (in FIFO mode).
•
NS16C2752 is Compatible to EXAR
XR16L2752, and Register Compatible to
Phillips SC16C752
•
•
•
•
Auto Hardware Flow Control (Auto-CTS, Auto-
RTS)
In the FIFO mode each channel is capable of
buffering 16 bytes (for NS16C2552) or 64 bytes (for
NS16C2752) of data in both the transmitter and
receiver. The receiver FIFO also has additional 3 bits
of error data per location. All FIFO control logic is on-
chip to minimize system software overhead and
maximize system efficiency.
Auto Software Flow Control (Xon, Xoff, and
Xon-any)
Fully Programmable Character Length (5, 6, 7,
or 8) with Even, Odd, or No Parity, Stop Bit
Adds or Deletes Standard Asynchronous
Communication Bits (Start, Stop, and Parity) to
or from the Serial Data
To improve the CPU processing bandwidth, the data
transfers between the DUART and the CPU can be
done using DMA controller. Signaling for DMA
transfers is done through two pins per channel
(TXRDY and RXRDY). The RXRDYfunction is
multiplexed on one pin with the OUT2 and BAUDOUT
functions. The configuration is through Alternate
Function Register.
•
Independently Controlled and Prioritized
Transmit and Receive Interrupts
•
•
•
Complete Line Status Reporting Capabilities
Line Break Generation and Detection
Internal Diagnostic Capabilities
The fundamental function of the UART is converting
between parallel and serial data. Serial-to-parallel
conversion is done on the UART receiver and
parallel-to-serial conversion is done on the
transmitter. The CPU can read the complete status of
each channel at any time. Status information reported
includes the type and condition of the transfer
operations being performed by the DUART, as well
as any error conditions (parity, overrun, framing, or
break interrupt).
–
Loopback Controls for Communications
Link Fault Isolation
–
Break, Parity, Overrun, Framing Error
Detection
•
Programmable Baud Generators Divide any
Input Clock by 1 to (216 - 1) and Generate the
16 X clock
•
•
•
IrDA v1.0 Wireless Infrared Encoder/Decoder
DMA Operation (TXRDY/RXRDY)
Concurrent Write to DUART Internal Register
Channels 1 and 2
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
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