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NS16C2752TVAX/NOPB PDF预览

NS16C2752TVAX/NOPB

更新时间： 2024-09-14 15:46:51
品牌 Logo 应用领域
德州仪器 - TI 通信时钟数据传输先进先出芯片外围集成电路
页数 文件大小 规格书
50页 1357K
描述
Dual UART with 64-byte FIFO and up to 5 Mbit/s Data Rate 44-PLCC -40 to 85

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NS16C2752TVAX/NOPB 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QFN
包装说明：QCCJ, LDCC44,.7SQ针数：44
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.73
其他特性：ALSO OPERATES AT 5V NOMINAL SUPPLY地址总线宽度：3
边界扫描：NO最大时钟频率：24 MHz
通信协议：ASYNC, BIT最大数据传输速率：0.625 MBps
外部数据总线宽度：8JESD-30 代码：S-PQCC-J44
JESD-609代码：e3长度：16.51 mm
低功率模式：YES湿度敏感等级：2A
串行 I/O 数：2端子数量：44
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装等效代码：LDCC44,.7SQ封装形状：SQUARE
封装形式：CHIP CARRIER峰值回流温度（摄氏度）：245
电源：3.3/5 V认证状态：Not Qualified
座面最大高度：4.57 mm子类别：Serial IO/Communication Controllers
最大供电电压：5.5 V最小供电电压：2.97 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：16.51 mm
uPs/uCs/外围集成电路类型：SERIAL IO/COMMUNICATION CONTROLLER, SERIALBase Number Matches：1

NS16C2752TVAX/NOPB 数据手册

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NS16C2552, NS16C2752  
www.ti.com  
SNLS238D –AUGUST 2006–REVISED APRIL 2013  
NS16C2552/NS16C2752 Dual UART with 16-byte/64-byte FIFO's and up to 5 Mbit/s Data  
Rate  
Check for Samples: NS16C2552, NS16C2752  
1
FEATURES  
•
•
Multi-Function Output Allows More Package  
Functions with Fewer I/O Pins  
2
•
Dual Independent UART  
44-PLCC or 48-TQFP Package  
•
•
•
Up to 5 Mbits/s Data Transfer Rate  
2.97 V to 5.50 V Operational Vcc  
DESCRIPTION  
The NS16C2552 and NS16C2752 are dual channel  
Universal  
5 V Tolerant I/Os in the Entire Supply Voltage  
Range  
Asynchronous  
Receiver/Transmitter  
•
•
Industrial Temperature: -40°C to 85°C  
(DUART). The footprint and the functions are  
compatible to the PC16552D, while new features are  
added to the UART device. These features include  
low voltage support, 5V tolerant inputs, enhanced  
features, enhanced register set, and higher data rate.  
Default Registers are Identical to the  
PC16552D  
•
NS16C2552/NS16C2752 is Pin-to-Pin  
Compatible to TI PC16552D, EXAR ST16C2552,  
XR16C2552, XR 16L2552, and Phillips  
SC16C2552B  
The two serial channels are completely independent  
of each other, except for a common CPU interface  
and crystal input. On power-up both channels are  
functionally identical to the PC16552D. Each channel  
can operate with on-chip transmitter and receiver  
FIFO’s (in FIFO mode).  
•
NS16C2752 is Compatible to EXAR  
XR16L2752, and Register Compatible to  
Phillips SC16C752  
•
•
•
•
Auto Hardware Flow Control (Auto-CTS, Auto-  
RTS)  
In the FIFO mode each channel is capable of  
buffering 16 bytes (for NS16C2552) or 64 bytes (for  
NS16C2752) of data in both the transmitter and  
receiver. The receiver FIFO also has additional 3 bits  
of error data per location. All FIFO control logic is on-  
chip to minimize system software overhead and  
maximize system efficiency.  
Auto Software Flow Control (Xon, Xoff, and  
Xon-any)  
Fully Programmable Character Length (5, 6, 7,  
or 8) with Even, Odd, or No Parity, Stop Bit  
Adds or Deletes Standard Asynchronous  
Communication Bits (Start, Stop, and Parity) to  
or from the Serial Data  
To improve the CPU processing bandwidth, the data  
transfers between the DUART and the CPU can be  
done using DMA controller. Signaling for DMA  
transfers is done through two pins per channel  
(TXRDY and RXRDY). The RXRDYfunction is  
multiplexed on one pin with the OUT2 and BAUDOUT  
functions. The configuration is through Alternate  
Function Register.  
•
Independently Controlled and Prioritized  
Transmit and Receive Interrupts  
•
•
•
Complete Line Status Reporting Capabilities  
Line Break Generation and Detection  
Internal Diagnostic Capabilities  
The fundamental function of the UART is converting  
between parallel and serial data. Serial-to-parallel  
conversion is done on the UART receiver and  
parallel-to-serial conversion is done on the  
transmitter. The CPU can read the complete status of  
each channel at any time. Status information reported  
includes the type and condition of the transfer  
operations being performed by the DUART, as well  
as any error conditions (parity, overrun, framing, or  
break interrupt).  
–
Loopback Controls for Communications  
Link Fault Isolation  
–
Break, Parity, Overrun, Framing Error  
Detection  
•
Programmable Baud Generators Divide any  
Input Clock by 1 to (216 - 1) and Generate the  
16 X clock  
•
•
•
IrDA v1.0 Wireless Infrared Encoder/Decoder  
DMA Operation (TXRDY/RXRDY)  
Concurrent Write to DUART Internal Register  
Channels 1 and 2  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2006–2013, Texas Instruments Incorporated  
1234567...50

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