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NS16C2552TVAX PDF预览

NS16C2552TVAX

更新时间: 2024-11-11 13:02:55
品牌 Logo 应用领域
美国国家半导体 - NSC 先进先出芯片
页数 文件大小 规格书
43页 907K
描述
IC 2 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQCC44, PLASTIC, LCC-44, Serial IO/Communication Controller

NS16C2552TVAX 技术参数

是否Rohs认证:不符合生命周期:Transferred
包装说明:PLASTIC, LCC-44Reach Compliance Code:not_compliant
HTS代码:8542.31.00.01风险等级:5.77
Is Samacsys:N地址总线宽度:3
边界扫描:NO最大时钟频率:24 MHz
通信协议:ASYNC, BIT数据编码/解码方法:NRZ
最大数据传输速率:0.625 MBps外部数据总线宽度:8
JESD-30 代码:S-PQCC-J44JESD-609代码:e0
长度:16.51 mm低功率模式:NO
湿度敏感等级:2A串行 I/O 数:2
端子数量:44最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC44,.7SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):220电源:3.3/5 V
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:Serial IO/Communication Controllers最大供电电压:5.5 V
最小供电电压:2.97 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:16.51 mmuPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, SERIAL
Base Number Matches:1

NS16C2552TVAX 数据手册

 浏览型号NS16C2552TVAX的Datasheet PDF文件第2页浏览型号NS16C2552TVAX的Datasheet PDF文件第3页浏览型号NS16C2552TVAX的Datasheet PDF文件第4页浏览型号NS16C2552TVAX的Datasheet PDF文件第5页浏览型号NS16C2552TVAX的Datasheet PDF文件第6页浏览型号NS16C2552TVAX的Datasheet PDF文件第7页 
PRELIMINARY  
August 2006  
NS16C2552/NS16C2752  
Dual UART with 16-byte/64-byte FIFO’s and up to  
5 Mbit/s Data Rate  
1.0 General Description  
2.0 Features  
n Dual independent UART  
The NS16C2552 and NS16C2752 are dual channel Univer-  
sal Asynchronous Receiver/Transmitter (DUART). The foot-  
print and the functions are compatible to the PC16552D,  
while new features are added to the UART device. These  
features include low voltage support, 5V tolerant inputs,  
enhanced features, enhanced register set, and higher data  
rate.  
n Up to 5 Mbits/s data transfer rate  
n 2.97 V to 5.50 V operational Vcc  
n 5 V tolerant I/Os in the entire supply voltage range  
n Industrial Temperature: -40˚C to 85˚C  
n Default registers are identical to the PC16552D  
n NS16C2552/NS16C2752 is pin-to-pin compatible to  
NSC PC16552D, EXAR ST16C2552, XR16C2552, XR  
16L2552, and Phillips SC16C2552B  
n NS16C2752 is compatible to EXAR XR16L2752, and  
register compatible to Phillips SC16C752  
n Auto Hardware Flow Control (Auto-CTS, Auto-RTS)  
n Auto Software Flow Control (Xon, Xoff, and Xon-any)  
n Fully programmable character length (5, 6, 7, or 8) with  
even, odd, or no parity, stop bit  
n Adds or deletes standard asynchronous communication  
bits (start, stop, and parity) to or from the serial data  
n Independently controlled and prioritized transmit and  
receive interrupts  
n Complete line status reporting capabilities  
n Line break generation and detection  
n Internal diagnostic capabilities  
The two serial channels are completely independent of each  
other, except for a common CPU interface and crystal input.  
On power-up both channels are functionally identical to the  
PC16552D. Each channel can operate with on-chip transmit-  
ter and receiver FIFO’s (in FIFO mode).  
In the FIFO mode each channel is capable of buffering 16  
bytes (for NS16C2552) or 64 bytes (for NS16C2752) of data  
in both the transmitter and receiver. The receiver FIFO also  
has additional 3 bits of error data per location. All FIFO  
control logic is on-chip to minimize system software over-  
head and maximize system efficiency.  
To improve the CPU processing bandwidth, the data trans-  
fers between the DUART and the CPU can be done using  
DMA controller. Signaling for DMA transfers is done through  
two pins per channel (TXRDY and RXRDY). The RXRDY  
function is multiplexed on one pin with the OUT2 and BAUD-  
OUT functions. The configuration is through Alternate Func-  
tion Register.  
— Loopback controls for communications link fault  
isolation  
— Break, parity, overrun, framing error detection  
n Programmable baud generators divide any input clock  
by 1 to (216 - 1) and generate the 16 X clock  
n IrDA v1.0 wireless Infrared encoder/decoder  
n DMA operation (TXRDY/RXRDY)  
n Concurrent write to DUART internal register channels 1  
and 2  
n Multi-function output allows more package functions with  
fewer I/O pins  
The fundamental function of the UART is converting be-  
tween parallel and serial data. Serial-to-parallel conversion  
is done on the UART receiver and parallel-to-serial conver-  
sion is done on the transmitter. The CPU can read the  
complete status of each channel at any time. Status infor-  
mation reported includes the type and condition of the trans-  
fer operations being performed by the DUART, as well as  
any error conditions (parity, overrun, framing, or break inter-  
rupt).  
The NS16C2552 and NS16C2752 include one program-  
mable baud rate generator for each channel. Each baud rate  
generator is capable of dividing the clock input by divisors of  
1 to (216 - 1), and producing a 16X clock for driving the  
internal transmitter logic and for receiver sampling circuitry.  
The NS16C2552 and NS16C2752 have complete MODEM-  
control capability, and a processor-interrupt system. The  
interrupts can be programmed by the user to minimize the  
processing required to handle the communications link.  
n 44-PLCC or 48-TQFP package  
© 2006 National Semiconductor Corporation  
DS202048  
www.national.com  

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