Datasheet > NS16C2552TVS

NS16C2552TVS

更新时间： 2024-09-15 20:35:51

品牌	Logo	应用领域
美国国家半导体 - NSC		/
页数	文件大小	规格书
44页	535K
描述
IC 2 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQFP48, TQFP-48, Serial IO/Communication Controller

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NS16C2552TVS 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
包装说明：	TQFP-48	Reach Compliance Code：	not_compliant
HTS代码：	8542.31.00.01	风险等级：	5.67
地址总线宽度：	3	边界扫描：	NO
最大时钟频率：	24 MHz	通信协议：	ASYNC, BIT
数据编码/解码方法：	NRZ	最大数据传输速率：	0.625 MBps
外部数据总线宽度：	8	JESD-30 代码：	S-PQFP-G48
JESD-609代码：	e0	长度：	7 mm
低功率模式：	NO	湿度敏感等级：	1
串行 I/O 数：	2	端子数量：	48
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	TFQFP
封装等效代码：	TQFP48,.35SQ	封装形状：	SQUARE
封装形式：	FLATPACK, THIN PROFILE, FINE PITCH	峰值回流温度（摄氏度）：	260
电源：	3.3/5 V	认证状态：	Not Qualified
座面最大高度：	1.2 mm	子类别：	Serial IO/Communication Controllers
最大供电电压：	5.5 V	最小供电电压：	2.97 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn85Pb15)	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	40	宽度：	7 mm
uPs/uCs/外围集成电路类型：	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL	Base Number Matches：	1

NS16C2552TVS 数据手册

June 3, 2009

NS16C2552/NS16C2752

Dual UART with 16-byte/64-byte FIFO's and up to 5 Mbit/s

Data Rate

1.0 General Description

2.0 Features

The NS16C2552 and NS16C2752 are dual channel Universal

Asynchronous Receiver/Transmitter (DUART). The footprint

and the functions are compatible to the PC16552D, while new

features are added to the UART device. These features in-

clude low voltage support, 5V tolerant inputs, enhanced fea-

tures, enhanced register set, and higher data rate.

Dual independent UART

■

Up to 5 Mbits/s data transfer rate

2.97 V to 5.50 V operational Vcc

5 V tolerant I/Os in the entire supply voltage range

Industrial Temperature: -40°C to 85°C

Default registers are identical to the PC16552D

The two serial channels are completely independent of each

other, except for a common CPU interface and crystal input.

On power-up both channels are functionally identical to the

PC16552D. Each channel can operate with on-chip transmit-

ter and receiver FIFO’s (in FIFO mode).

NS16C2552/NS16C2752 is pin-to-pin compatible to NSC

PC16552D, EXAR ST16C2552, XR16C2552, XR

16L2552, and Phillips SC16C2552B

NS16C2752 is compatible to EXAR XR16L2752, and

■

In the FIFO mode each channel is capable of buffering 16

bytes (for NS16C2552) or 64 bytes (for NS16C2752) of data

in both the transmitter and receiver. The receiver FIFO also

has additional 3 bits of error data per location. All FIFO control

logic is on-chip to minimize system software overhead and

maximize system efficiency.

Auto Hardware Flow Control (Auto-CTS, Auto-RTS)

■

Auto Software Flow Control (Xon, Xoff, and Xon-any)

Fully programmable character length (5, 6, 7, or 8) with

even, odd, or no parity, stop bit

Adds or deletes standard asynchronous communication

bits (start, stop, and parity) to or from the serial data

■

To improve the CPU processing bandwidth, the data transfers

between the DUART and the CPU can be done using DMA

controller. Signaling for DMA transfers is done through two

pins per channel (TXRDY and RXRDY). The RXRDY function

is multiplexed on one pin with the OUT2 and BAUDOUT func-

tions. The configuration is through Alternate Function Regis-

ter.

Independently controlled and prioritized transmit and

receive interrupts

■

Complete line status reporting capabilities

■

Line break generation and detection

Internal diagnostic capabilities

— Loopback controls for communications link fault

isolation

The fundamental function of the UART is converting between

parallel and serial data. Serial-to-parallel conversion is done

on the UART receiver and parallel-to-serial conversion is

done on the transmitter. The CPU can read the complete sta-

tus of each channel at any time. Status information reported

includes the type and condition of the transfer operations be-

ing performed by the DUART, as well as any error conditions

(parity, overrun, framing, or break interrupt).

— Break, parity, overrun, framing error detection

Programmable baud generators divide any input clock by

1 to (2¹⁶- 1) and generate the 16 X clock

■

IrDA v1.0 wireless Infrared encoder/decoder

■

DMA operation (TXRDY/RXRDY)

Concurrent write to DUART internal register channels 1

and 2

The NS16C2552 and NS16C2752 include one programmable

baud rate generator for each channel. Each baud rate gen-

erator is capable of dividing the clock input by divisors of 1 to

(2¹⁶- 1), and producing a 16X clock for driving the internal

transmitter logic and for receiver sampling circuitry. The

NS16C2552 and NS16C2752 have complete MODEM-con-

trol capability, and a processor-interrupt system. The inter-

rupts can be programmed by the user to minimize the

processing required to handle the communications link.

Multi-function output allows more package functions with

fewer I/O pins

■

44-PLCC or 48-TQFP package

■

202048

www.national.com

12 3 4 5 6 7...44

中文翻译

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与NS16C2552TVS相关器件

型号	品牌	获取价格	描述	数据表
NS16C2552TVS/NOPB	TI	获取价格	具有 16 字节 FIFO、数据速率高达 5 兆位/秒的双路 UART \| PFB \| 4
NS16C2552TVSX	NSC	获取价格	IC 2 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQFP48, TQFP-48, Serial IO/Communication
NS16C2552TVSX/NOPB	TI	获取价格	具有 16 字节 FIFO、数据速率高达 5 兆位/秒的双路 UART \| PFB \| 4
NS16C2752	NSC	获取价格	Dual UART with 16-byte/64-byte FIFOs and up to 5 Mbit/s Data Rate
NS16C2752	TI	获取价格	具有 64 字节 FIFO、数据速率高达 5 兆位/秒的双路 UART
NS16C2752TVA	NSC	获取价格	Dual UART with 16-byte/64-byte FIFOs and up to 5 Mbit/s Data Rate
NS16C2752TVA/NOPB	TI	获取价格	具有 64 字节 FIFO、数据速率高达 5 兆位/秒的双路 UART \| FN \| 44
NS16C2752TVAX/NOPB	TI	获取价格	Dual UART with 64-byte FIFO and up to 5 Mbit/s Data Rate 44-PLCC -40 to 85
NS16C2752TVS/NOPB	TI	获取价格	具有 64 字节 FIFO、数据速率高达 5 兆位/秒的双路 UART \| PFB \| 4
NS16C2752TVSX/NOPB	TI	获取价格	具有 64 字节 FIFO、数据速率高达 5 兆位/秒的双路 UART \| PFB \| 4

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