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NM27C256VE120X PDF预览

NM27C256VE120X

更新时间: 2024-11-16 13:11:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 存储内存集成电路可编程只读存储器OTP只读存储器电动程控只读存储器
页数 文件大小 规格书
11页 114K
描述
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NM27C256VE120X 数据手册

 浏览型号NM27C256VE120X的Datasheet PDF文件第2页浏览型号NM27C256VE120X的Datasheet PDF文件第3页浏览型号NM27C256VE120X的Datasheet PDF文件第4页浏览型号NM27C256VE120X的Datasheet PDF文件第5页浏览型号NM27C256VE120X的Datasheet PDF文件第6页浏览型号NM27C256VE120X的Datasheet PDF文件第7页 
July 1998  
NM27C256  
262,144-Bit (32K x 8) High Performance CMOS EPROM  
The NM27C256 is one member of a high density EPROM Family  
which range in densities up to 4 Mb.  
General Description  
The NM27C256 is a 256K Electrically Programmable Read Only  
Memory. It is manufactured in Fairchild’s latest CMOS split gate  
EPROM technology which enables it to operate at speeds as fast  
as 90 ns access time over the full operating range.  
Features  
High performance CMOS  
90 ns access time  
The NM27C256 provides microprocessor-based systems exten-  
JEDEC standard pin configuration  
sive storage capacity for large portions of operating system and  
— 28-pin PDIP package  
application software. Its 90 ns access time provides high speed  
— 32-pin chip carrier  
operation with high-performance CPUs. The NM27C256 offers a  
— 28-pin CERDIP package  
single chip solution for the code storage requirements of 100%  
Drop-in replacement for 27C256 or 27256  
firmware-based equipment. Frequently-used software routines  
are quickly executed from EPROM storage, greatly enhancing  
system utility.  
Manufacturer’s identification code  
The NM27C256 is configured in the standard EPROM pinout  
which provides an easy upgrade path for systems which are  
currently using standard EPROMs.  
Block Diagram  
Data Outputs O - O  
0
7
V
CC  
GND  
V
PP  
OE  
Output Enable  
and Chip Enable Logic  
Output  
Buffers  
CE/PGM  
Y Decoder  
Y Gating  
A
- A  
14  
0
Address  
Inputs  
X Decoder  
DS010833-1  
1
© 1998 Fairchild Semiconductor Corporation  
www.fairchildsemi.com  

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