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NLAST4051_06

更新时间： 2024-11-20 03:46:23
品牌 Logo 应用领域
安森美 - ONSEMI 解复用器
页数 文件大小 规格书
12页 152K
描述
Analog Multiplexer/ Demultiplexer

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NLAST4051_06 数据手册

 浏览型号NLAST4051_06的Datasheet PDF文件第2页浏览型号NLAST4051_06的Datasheet PDF文件第3页浏览型号NLAST4051_06的Datasheet PDF文件第4页浏览型号NLAST4051_06的Datasheet PDF文件第5页浏览型号NLAST4051_06的Datasheet PDF文件第6页浏览型号NLAST4051_06的Datasheet PDF文件第7页 
NLAST4051  
Analog Multiplexer/  
Demultiplexer  
TTL Compatible, Single−Pole, 8−Position  
Plus Common Off  
http://onsemi.com  
MARKING  
The NLAST4051 is an improved version of the MC14051 and  
MC74HC4051 fabricated in sub−micron Silicon Gate CMOS technology  
for lower R  
resistance and improved linearity with low current.  
DIAGRAMS  
DS(on)  
This device may be operated either with a single supply or dual supply up  
to 3 V to pass a 6 V signal without coupling capacitors.  
16  
PP  
When operating in single supply mode, it is only necessary to tie  
SOIC−16  
D SUFFIX  
CASE 751B  
NLAST4051  
AWLYWW  
V
, pin 7 to ground. For dual supply operation, V is tied to a  
EE  
EE  
negative voltage, not to exceed maximum ratings. Translation is  
provided in the device, the Address and Inhibit are standard TTL level  
compatible. For CMOS compatibility see NLAS4051. Pin for pin  
compatible with all industry standard versions of ‘4051.’  
1
1
16  
AST  
4051  
ALYWG  
G
TSSOP−16  
DT SUFFIX  
CASE 948F  
Features  
• Improved R  
Specifications  
DS(on)  
1
• Pin for Pin Replacement for MAX4051 and MAX4051A  
− One Half the Resistance Operating at 5.0 V  
• Single or Dual Supply Operation  
1
16  
− Single 3.0 − 5.0 V Operation, or Dual 3 V Operation  
− With V of 3.0 to 3.3 V, Device Can Interface with 1.8 V Logic,  
− No Translators Needed  
− Address and Inhibit Logic are Over−Voltage Tolerant and May Be  
QSOP−16  
QS SUFFIX  
CASE 492  
CC  
NLAST  
4051  
ALYW  
1
− Driven Up +6 V Regardless of V  
CC  
1
• Address and Inhibit Pins Standard TTL Compatible  
− Greatly Improved Noise Margin Over MAX4051 and MAX4051A  
− True TTL Compatibility V = 0.8 V, V = 2.0 V  
A
WL, L  
Y
= Assembly Location  
= Wafer Lot  
= Year  
IL  
IH  
• Improved Linearity Over Standard HC4051 Devices  
• Popular SOIC, and Space Saving TSSOP, and QSOP 16 Pin  
Packages  
WW, W = Work Week  
G
= Pb−Free Package  
(Note: Microdot may be in either location)  
• Pb−Free Packages are Available*  
V
NO  
15  
NO  
NO  
13  
NO ADD ADD ADD  
6 C B A  
CC  
2
4
0
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
16  
14  
12  
11  
10  
9
dimensions section on page 10 of this data sheet.  
1
2
3
4
5
6
Inhibit  
7
8
NO  
NO COM NO  
NO  
V
EE  
GND  
1
3
7
5
Figure 1. Pin Connection  
(Top View)  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
© Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
April, 2006 − Rev. 4  
NLAST4051/D  
1234567...12

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