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MV76100_1

更新时间: 2024-09-17 05:51:15
品牌 Logo 应用领域
迈威 - MARVELL /
页数 文件大小 规格书
2页 323K
描述
Discovery Innovation Series

MV76100_1 数据手册

 浏览型号MV76100_1的Datasheet PDF文件第2页 
Marvell MV76100 SoC with Sheeva Technology  
Discovery Innovation Series  
PRODUCT OVERVIEW  
The MV76100 is a high-performance, low-power, highly integrated processor with the Marvell® Sheeva™ CPU technology  
included. The Sheeva core is an ARMv5TE-compliant CPU core. Built on Marvell’s innovative Discovery™ system controller  
platform, the MV76100 is a complete system-on-chip (SoC) solution. Optimized for cost-sensitive applications, the  
MV76100 is ideally suited to a wide range of applications ranging from small and medium business (SMB) routers, switches  
and single board computers, to high-volume laser printer applications.  
The MV76100 offers unparalleled integration that makes system design simple and cost efficient. The SoC integrates:  
Dual-issue CPU with Vector Floating Point (VFP) support  
600-800 MHz operating speed  
32KB-Instruction and 32KB-Data 4-way, set-associative L1 cache  
256KB unified 4-way, set-associative L2 cache  
32-bit high bandwidth DDR2 memory interface (up to 800 MHz data rate)  
Two Gigabit Ethernet MACs with interface options  
Two PCI-Express ports (one port is x4 or Quad x1, second port is x1)  
Three USB 2.0 ports with integrated PHYs  
One SATA 2.0 port with integrated PHYs  
Security engine  
The innovative, on-chip crossbar architecture with any-to-any connectivity enables concurrent transactions among multiple  
units that results in high system throughput allowing system designers to create high-performance scalable systems.  
Tightly integrated CPU and memory controller significantly improves application performance.  
BLOCK DIAGRAM  
Sheeva™ CPU Core  
Dual Issue w/FPU  
32KB-I, 32KB-D  
600-800MHz  
32-bit  
DDR2-800  
with ECC  
DDR II  
Controller  
256KB L2  
2 x GE  
MAC  
PCI-E  
PCI-E  
x 4 or  
quad x 1  
SATA II  
with PHY  
System Crossbar  
x 1  
3 x USB 2.0  
with PHY  
Device bus  
NAND, NOR  
3 x UARTs  
TWSI, SPI  
Security  
Engine  
4 IDMA  
+ 2 XOR  
32b  
Fig 1. MV76100 SoC Block Diagram  

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