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MU9C4485L-70TCC

更新时间： 2024-01-09 18:06:22
品牌 Logo 应用领域
MUSIC 存储内存集成电路静态存储器双倍数据速率局域网
页数 文件大小 规格书
28页 161K
描述
WidePort LANCAM㈢ Family

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中文翻译

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MU9C4485L-70TCC 技术参数

是否Rohs认证： 不符合生命周期：Contact Manufacturer
包装说明：QFP, QFP80,.64SQReach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.32.00.41
风险等级：5.8Is Samacsys：N
最长访问时间：52 ns其他特性：LANCAM
JESD-30 代码：S-PQFP-G80JESD-609代码：e0
内存密度：262144 bit内存集成电路类型：CONTENT ADDRESSABLE SRAM
内存宽度：64湿度敏感等级：3
功能数量：1端子数量：80
字数：4096 words字数代码：4000
工作模式：ASYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：4KX64
封装主体材料：PLASTIC/EPOXY封装代码：QFP
封装等效代码：QFP80,.64SQ封装形状：SQUARE
封装形式：FLATPACK并行/串行：PARALLEL
电源：3.3 V认证状态：Not Qualified
最大待机电流：0.002 A子类别：SRAMs
最大压摆率：0.265 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.635 mm
端子位置：QUADBase Number Matches：1

MU9C4485L-70TCC 数据手册

 浏览型号MU9C4485L-70TCC的Datasheet PDF文件第3页浏览型号MU9C4485L-70TCC的Datasheet PDF文件第4页浏览型号MU9C4485L-70TCC的Datasheet PDF文件第5页浏览型号MU9C4485L-70TCC的Datasheet PDF文件第7页浏览型号MU9C4485L-70TCC的Datasheet PDF文件第8页浏览型号MU9C4485L-70TCC的Datasheet PDF文件第9页 
WidePort LANCAM® Family  
FUNCTIONAL DESCRIPTION Continued  
address of the Highest-Priority Matching location in that  
device, concatenated with its page address, along with  
flags indicating internal match, multiple match, and full.  
When the Status register is read with a Command Read  
cycle, the device with the Highest-priority match will  
respond, outputting the System Match address to the DQ  
bus. The internal Match (/MA) and Multiple match (/MM)  
flags are also output on pins. Another set of flags (/MF  
and /FF) that are qualified by the match and full flags of  
previous devices in the system are also available directly  
on output pins, and are independently daisy-chained to  
provide System Match and Full flags in vertically cascaded  
LANCAM arrays. In such arrays, if no match occurs during  
a comparison, read access to the memory and all the  
registers except the Next Free register is denied to prevent  
device contention. In a daisy chain, all devices will respond  
to Command and Data Write cycles, depending on the  
conditions shown in Tables 6a and 6b, unless the operation  
involves the Highest-Priority Match address or the Next  
Free address; in which case, only the specific device  
having the Highest-Priority match or the Next Free  
address will respond.  
A Page Address register in each device simplifies vertical  
expansion in systems using more than one LANCAM. This  
register is loaded with a specific device address during  
system initialization, which then serves as the higher-order  
address bits. A Device Select register allows the user to  
target a specific device within a vertically cascaded system  
by setting it equal to the Page Address Register value, or  
to address all the devices in a string at the same time by  
setting the Device Select value to FFFFH.  
Figure 1a shows expansion using a daisy chain. Note that  
system flags are generated without the need for external  
logic. The Page Address register allows each device in the  
vertically cascaded chain to supply its own address in the  
event of a match, eliminating the need for an external priority  
encoder to calculate the complete Match address at the  
expense of the ripple-through time to resolve the highest-  
priority match. The Full flag daisy-chaining allows  
Associative writes using a Move to Next Free Address  
instruction which does not need a supplied address.  
Figure 1b shows an external PLD implementation of a simple  
priority encoder that eliminates the daisy chain ripple-  
through delays for systems requiring maximum performance  
from many CAMS.  
Vcc  
Vcc  
32  
D Q 31-0  
/E  
D Q 31-0  
/E  
/MI  
/FI  
/MI  
PLD  
W id e p o r t  
L AN C AM  
/W  
/W  
Wide Port  
/FF  
LANCAM  
/MA  
/C M  
/EC  
/C M  
/EC  
/MF  
D Q 31-0  
/E  
/MI  
/FI  
/MI  
W id e p o r t  
L AN C AM  
Wide Port  
LANCAM  
/MA  
/W  
/FF  
/C M  
/EC  
/MF  
/MI  
Wide Port  
LANCAM  
/MA  
D Q 31-0  
/E  
/MI  
/FI  
/MI  
Wide Port  
W id e p o r t  
L AN C AM  
/W  
SYSTEM F U L L  
LANCAM  
/MA  
/FF  
/C M  
/EC  
SY STEM  
SYSTE M MATC H  
/MF  
M ATCH  
Figure 1a: Vertical Cascading  
Figure 1b: External Prioritizing  
Rev. 2  
6
1...3456789...28

中文翻译

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