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MU9C4485L-70TCC PDF预览

MU9C4485L-70TCC

更新时间: 2024-02-21 16:41:39
品牌 Logo 应用领域
MUSIC 存储内存集成电路静态存储器双倍数据速率局域网
页数 文件大小 规格书
28页 161K
描述
WidePort LANCAM㈢ Family

MU9C4485L-70TCC 技术参数

是否Rohs认证: 不符合生命周期:Contact Manufacturer
包装说明:QFP, QFP80,.64SQReach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.41
风险等级:5.8Is Samacsys:N
最长访问时间:52 ns其他特性:LANCAM
JESD-30 代码:S-PQFP-G80JESD-609代码:e0
内存密度:262144 bit内存集成电路类型:CONTENT ADDRESSABLE SRAM
内存宽度:64湿度敏感等级:3
功能数量:1端子数量:80
字数:4096 words字数代码:4000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:4KX64
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装等效代码:QFP80,.64SQ封装形状:SQUARE
封装形式:FLATPACK并行/串行:PARALLEL
电源:3.3 V认证状态:Not Qualified
最大待机电流:0.002 A子类别:SRAMs
最大压摆率:0.265 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.635 mm
端子位置:QUADBase Number Matches:1

MU9C4485L-70TCC 数据手册

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WidePort LANCAM® Family  
PIN DESCRIPTIONS  
All signals are implemented in CMOS technology with TTL levels. Signal names that start with a slash (“/”) are active LOW. Inputs  
should never be left floating. The CAM architecture draws large currents during compare operations, mandating the use of good layout  
and bypassing techniques. Refer to the Electrical Characteristics section for more information.  
of the device (/MF=/MI). /MF is HIGH if there is no match  
or when the daisy chain is disabled (/E goes HIGH when  
/EC was HIGH on the previous falling edge of /E). The  
System Match flag is the /MF pin of the last device in  
the daisy chain. /MF will be reset when the active  
configuration register set is changed.  
/E (Chip Enable, Input, TTL)  
The /E input enables the device while LOW. The falling  
edge registers the control signals /W, /CM, /EC. The rising  
edge locks the daisy chain, turns off the DQ pins, and clocks  
the Destination and Source Segment counters. The four  
cycle types enabled by /E are shown in Table 2.  
/MI (Match Input, Input, TTL)  
/W (Write Enable, Input, TTL)  
The /MI input prioritizes devices in vertically cascaded  
systems. It is connected to the /MF output of the previous  
device in the daisy chain. The /MI pin on the first device in  
the chain must be tied HIGH.  
The /W input selects the direction of data flow during a  
device cycle. /W LOW selects a Write cycle and /W HIGH  
selects a Read cycle.  
/CM (Data/Command Select, Input, TTL)  
The /CM input selects whether the input signals on  
DQ31–0 are data or commands. /CM LOW selects Command  
cycles and /CM HIGH selects Data cycles.  
/MA (Device Match Flag, Output, TTL)  
The /MA output is LOW when one or more valid matches  
occur during the current or the last previous compare  
cycle. The /MA output is not qualified by /EC or /MI,  
and reflects the match flag from that specific device’s  
Status register. /MA will be reset when the active register  
set is changed.  
/EC (Enable Daisy Chain, Input, TTL)  
The /EC signal performs two functions. The /EC input  
enables the /MF output to show the results of a comparison,  
as shown in Figure 6. If /EC is LOW at the falling edge of /E  
in a given cycle, the /MF output is enabled. Otherwise, the  
/MF output is held HIGH. The /EC signal also enables the  
/MF–/MI daisy chain, which serves to select the device  
with the highest-priority match in a string of LANCAMs.  
Tables 6a and 6b explain the effect of the /EC signal on a  
device with or without a match in both Standard and  
Enhanced modes. /EC must be HIGH during initialization.  
/MM (Device Multiple Match Flag, Output, TTL)  
The /MM output is LOW when more than one valid  
match occurs during the current or the last previous  
compare cycle. The /MM output is not qualified by /EC  
or /MI, and reflects the multiple match flag from that  
specific device’s Status register. /MM will be reset when  
the active register set is changed.  
/FF (Full Flag, Output, TTL)  
DQ31–0 (Data Bus, Three-state I/O, TTL)  
The DQ31–0 lines convey data, commands, and status to  
and from the WidePort LANCAM, as shown in Table 3. /W  
and /CM control the direction and nature of the information  
that flows to or from the device. When /E is HIGH, DQ31–0 go  
to HIGH-Z.  
If enabled in the Control register, the /FF output goes LOW  
when no empty memory locations exist within the device  
(and in the daisy chain above the device as indicated by  
the /FI pin). The System Full flag is the /FF pin of the last  
device in the daisy chain, and the Next Free address resides  
in the device with /FI LOW and /FF HIGH. If disabled in the  
Control register, the /FF output only depends on the /FI  
input (/FF = /FI).  
/MF (Match Flag, Output, TTL)  
The /MF output goes LOW when one or more valid  
matches occur during a compare cycle. /MF becomes  
valid after /E goes HIGH on the cycle that enables the  
daisy chain (on the first cycle that /EC is registered LOW  
by the previous falling edge of /E; see Figure 6). In a  
daisy chain, valid match(es) in higher priority devices  
are passed from the /MI input to /MF. If the daisy chain  
is enabled but the match flag is disabled in the Control  
register, the /MF output only depends on the /MI input  
/FI (Full Input, Input, TTL)  
The /FI input generates a CAM-Memory-System-Full  
indication in vertically cascaded systems. It is connected  
to the /FF output of the previous device in the daisy chain.  
The /FI pin on the first device in a chain must be tied LOW.  
3
Rev. 2  

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