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MU9C4485L-70TCC PDF预览

MU9C4485L-70TCC

更新时间： 2024-02-29 00:32:52
品牌 Logo 应用领域
MUSIC 存储内存集成电路静态存储器双倍数据速率局域网
页数 文件大小 规格书
28页 161K
描述
WidePort LANCAM㈢ Family

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中文翻译

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MU9C4485L-70TCC 技术参数

是否Rohs认证： 不符合生命周期：Contact Manufacturer
包装说明：QFP, QFP80,.64SQReach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.32.00.41
风险等级：5.8Is Samacsys：N
最长访问时间：52 ns其他特性：LANCAM
JESD-30 代码：S-PQFP-G80JESD-609代码：e0
内存密度：262144 bit内存集成电路类型：CONTENT ADDRESSABLE SRAM
内存宽度：64湿度敏感等级：3
功能数量：1端子数量：80
字数：4096 words字数代码：4000
工作模式：ASYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：4KX64
封装主体材料：PLASTIC/EPOXY封装代码：QFP
封装等效代码：QFP80,.64SQ封装形状：SQUARE
封装形式：FLATPACK并行/串行：PARALLEL
电源：3.3 V认证状态：Not Qualified
最大待机电流：0.002 A子类别：SRAMs
最大压摆率：0.265 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.635 mm
端子位置：QUADBase Number Matches：1

MU9C4485L-70TCC 数据手册

 浏览型号MU9C4485L-70TCC的Datasheet PDF文件第1页浏览型号MU9C4485L-70TCC的Datasheet PDF文件第2页浏览型号MU9C4485L-70TCC的Datasheet PDF文件第3页浏览型号MU9C4485L-70TCC的Datasheet PDF文件第5页浏览型号MU9C4485L-70TCC的Datasheet PDF文件第6页浏览型号MU9C4485L-70TCC的Datasheet PDF文件第7页 
WidePort LANCAM® Family  
PIN DESCRIPTIONS Continued  
/RESET (Reset, Input, TTL)  
VCC, GND (Positive Power Supply, Ground)  
These pins are the power supply connections to the  
WidePort LANCAM. VCC must meet the voltage supply  
requirements in the Operating Conditions section relative  
to the GND pins, which are at 0 Volts (system reference  
potential), for correct operation of the device. All the  
ground and power pins must be connected to their  
respective planes with adequate bulk and high frequency  
bypassing capacitors in close proximity to the device.  
The MU9C2485A/L and MU9C1485A/L are compatible  
with the original MU9C1485 connections, and may be  
operated at -90 or slower switching characteristics  
without the GND connections on pins 1, 2, 20, 21, 22, 41,  
42, 60, 61, and 62.  
/RESET must be driven LOW to place the device in a known  
state before operation, which will reset the device to the  
conditions shown in Table 5. The /RESET pin should be  
driven by TTL levels, not directly by an RC timeout. /E  
must be kept HIGH during /RESET.  
TEST1, TEST2 (Test, Input, TTL)  
These pins enable MUSIC production test modes that are  
not usable in an application. They should be connected to  
ground, either directly or through a pull-down resistor, or  
they may be left unconnected. These pins may not be  
implemented on all versions of these products.  
FUNCTIONAL DESCRIPTION  
The WidePort LANCAM is a content-addressable  
memory (CAM) with 32-bit I/O for network address  
filtering, virtual memory, data compression, caching, and  
table lookup applications. The memory consists of static  
CAM, organized in 64-bit data fields. Each data field can  
be partitioned into a CAM and a RAM subfield on 16-bit  
boundaries. The contents of the memory can be randomly  
accessed or associatively accessed by the use of a  
compare. During automatic comparison cycles, data in  
the Comparand register is automatically compared with  
the “Valid” entries in the memory array. The Device ID can be  
read using a TCO PS instruction (see Table 13).  
globally configurable into CAM and RAM segments on  
16-bit boundaries, as described in US Patent 5,383,146  
assigned to MUSIC Semiconductors. Seven different  
CAM/RAM splits are possible, with the CAM width  
going from one to four segments, and the remaining RAM  
width going from three to zero segments. Finer resolution  
on compare width is possible by invoking a mask register  
during a compare, which does global masking on a bit  
basis. The CAM subfield contains the associative data,  
which enters into compares, while the RAM subfield  
contains the associated data, which is not compared. In  
LAN bridges, the RAM subfield can hold, for example,  
port-address and aging information related to the  
destination or source address information held in the  
CAM subfield of a given location. In a translation  
application, the CAM field can hold the dictionary  
entries, while the RAM field holds the translations, with  
almost instantaneous response.  
The data inputs and outputs of the WidePort LANCAM  
are multiplexed for data and instructions over a 32-bit  
I/O bus. Internally, data is handled on a 64-bit basis,  
since the Comparand register, the mask registers, and  
each memory entry are 64 bits wide. Memory entries are  
/W  
/CM  
Cycle Type  
“f” Bit  
DQ31–16  
DQ15–0  
XXXX  
LOW  
LOW  
Command write  
0
1
Non-TCO Instruction  
Non-TCO Instruction  
Absolute Address  
XXXX  
0
TCO Instruction (Read register)*  
TCO Instruction (Write register)  
Status Register bits 31–16  
Status Register bits 31–16†  
Data to CR, MRX, Mem.  
1
Value to Register  
Status Register bits 15–0  
Register contents*  
Data to CR, MRX, Mem.  
Data from CR, MRX, Mem.  
HIGH  
LOW  
Command read  
TCO 2nd cycle  
Data write  
X
X
X
X
LOW  
HIGH  
HIGH  
HIGH  
Data read  
Data from CR, MRX, Mem.  
*
Notes:  
A CW of a TCO Instruction with the “f” bit set to 0 sets up a Register read in the following cycle. The  
following cycle must be a Command Read cycle, otherwise the register read will be cancelled.  
†
Upper 16 bits will be Status Register bits 31–16, except for a read of the Page Address register, in which  
case they will be all zeros.  
Table 3: DQ Bus Multiplexing  
4
Rev. 2  
1234567...28

中文翻译

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