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MT90810AK3

更新时间： 2024-09-24 19:54:55
品牌 Logo 应用领域
加拿大卓联 - ZARLINK /
页数 文件大小 规格书
40页 494K
描述
Telecom Circuit, 1-Func, CMOS, PQFP100, 14 X 20 MM, 2.80 MM HEIGHT, LEAD FREE, PLASTIC, MQFP-100

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MT90810AK3 技术参数

是否Rohs认证： 符合生命周期：Obsolete
包装说明：QFP, QFP100,.8X1.0Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.19
JESD-30 代码：R-PQFP-G100JESD-609代码：e6
长度：20 mm湿度敏感等级：3
功能数量：1端子数量：100
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：QFP
封装等效代码：QFP100,.8X1.0封装形状：RECTANGULAR
封装形式：FLATPACK峰值回流温度（摄氏度）：260
电源：5 V认证状态：Not Qualified
座面最大高度：2.8 mm子类别：Other Telecom ICs
标称供电电压：5 V表面贴装：YES
技术：CMOS电信集成电路类型：TELECOM CIRCUIT
温度等级：COMMERCIAL端子面层：TIN BISMUTH
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：14 mmBase Number Matches：1

MT90810AK3 数据手册

 浏览型号MT90810AK3的Datasheet PDF文件第2页浏览型号MT90810AK3的Datasheet PDF文件第3页浏览型号MT90810AK3的Datasheet PDF文件第4页浏览型号MT90810AK3的Datasheet PDF文件第5页浏览型号MT90810AK3的Datasheet PDF文件第6页浏览型号MT90810AK3的Datasheet PDF文件第7页 
CMOS MT90810  
Flexible MVIP Interface Circuit  
Data Sheet  
August 2005  
Features  
•
•
MVIPand ST-BUScompliant  
Ordering Information  
MVIP Enhanced Switching with 384x384 channel  
capacity (256 MVIP channels; 128 local  
channels)  
MT90810AK3 100 Pin PQFP*  
*Pb Free Sn-Bi Plating  
Trays  
•
•
On-chip PLL for MVIP master/slave operation  
0°C to +70°C  
Local output clocks of 2.048,4.096,8.192 MHz  
with programmable polarity  
Local serial interface is programmable to 2.048,  
4.096 or 8.192 Mb/s with associated clock  
outputs  
Additional control output stream  
Per-channel message mode  
•
•
Centralized voice processing systems  
Voice/Data multiplexer  
•
Description  
•
•
•
Zarlink’s MT90810 is a Flexible MVIP Interface Circuit  
(FMIC). The MVIP (Multi-Vendor Integration Protocol)  
compliant device provides a complete MVIP compliant  
interface between the MVIP Bus and a wide variety of  
processors, telephony interfaces and other circuits. A  
built-in digital time-slot switch provides MVIP enhanced  
switching between the full MVIP Bus and any  
combination of up to 128 full duplex local channels of  
64 kbps each. An 8 bit microprocessor port allows real-  
time control of switching and programming of device  
configuration. On-board clock circuitry, including both  
analog and digital phase-locked loops, supports all  
MVIP clock modes. The local interface supports PCM  
rates of 2.048, 4.096 and 8.192 Mb/s, as well as  
parallel DMA through the microprocessor port.  
Two independently programmable groups of up to  
12 framing signals each  
Motorola non-multiplexed or Intel  
multiplexed/non-multiplexed microprocessor  
interface  
•
Applications  
•
•
•
Medium size digital switch matrices  
MVIP interface functions  
Serial bus control and monitoring  
EX_8KA  
X2 X1/CLKIN PLL_LO PLL_LI  
FRAME  
EX_8KB  
SEC8K  
C4b  
CLK2  
CLK4  
CLK8  
RESET  
Timing and Clock Control  
C2o  
(Oscillator and Analog & Digital PLLs)  
F0b  
Enhanced Switch  
DSo[0:7]  
DSi[0:7]  
LDO[0:3]  
LDI[0:3]  
CSTo  
Data Memory  
S-P/  
P-S  
FGA[0:11]  
FGB[0:11]  
Programmable  
Framing Signals  
Connection Memory  
TCK  
TMS  
TDI  
JTAG  
ERR  
Microprocessor Interface  
TDO  
AD[0:7] A[0:1] ALE WR/ RD/ CS RDY/ DREQ[0:1] DACK[0:1]  
DS  
R/W  
DTACK  
Figure 1 - Functional Block Diagram  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 1997-2005, Zarlink Semiconductor Inc. All Rights Reserved.  
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