MT90823
3 V Large Digital Switch
Data Sheet
July 2005
Features
•
2,048 × 2,048 channel non-blocking switching at
Ordering Information
8.192 Mb/s
MT90823AP
MT90823AL
MT90823AB
MT90823AG
84 Pin PLCC
100 Pin MQFP
100 Pin LQFP
120 Pin BGA
Tubes
Trays
Trays
Trays
Trays
Tubes
Trays
•
Per-channel variable or constant throughput
delay
Automatic identification of ST-BUS/GCI interfaces
•
•
MT90823AB1 100 Pin LQFP*
MT90823AP1 84 Pin PLCC*
Accept ST-BUS streams of 2.048, 4.096 or
8.192 Mb/s
MT90823AL1
100 Pin MQFP*
*Pb Free Matte Tin
•
•
•
•
•
Automatic frame offset delay measurement
Per-stream frame delay offset programming
Per-channel high impedance output control
Per-channel message mode
-40°C to +85°C
Applications
•
•
•
•
•
•
Medium and large switching platforms
CTI application
Voice/data multiplexer
Control interface compatible to Motorola non-
multiplexed CPUs
•
•
Connection memory block programming
3.3 V local I/O with 5 V tolerant inputs and TTL-
compatible outputs
Digital cross connects
ST-BUS/GCI interface functions
Support IEEE 802.9a standard
•
IEEE-1149.1 (JTAG) Test Port
V
V
SS
ODE
TMS
TDI TDO TCK TRST
IC
RESET
DD
Test Port
Loopback
STo0
STo1
STo2
STo3
STo4
STo5
STo6
STo7
STo8
STo9
STo10
STo11
STo12
STo13
STo14
STo15
STi0
STi1
STi2
Serial
to
Parallel
to
STi3
STi4
Output
STi5
Parallel
Multiple Buffer
Data Memory
STi6
MUX
Serial
STi7
Converter
STi8
Converter
STi9
STi10
STi11
STi12
STi13
STi14
STi15
Connection
Memory
Internal
Registers
Timing
Unit
Microprocessor Interface
CLK F0i FE/ WFPS
HCLK
AS/ IM DS/
CS R/W
/WR
D15-D8/ CSTo
A7-A0 DTA
ALE
RD
AD7-AD0
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.