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MT90820 PDF预览

MT90820

更新时间: 2024-01-27 08:46:33
品牌 Logo 应用领域
MITEL /
页数 文件大小 规格书
10页 73K
描述
CMOS ST-BUS? FAMILY Large Digital Switch (LDX)

MT90820 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:QCCJ, LDCC84,1.2SQReach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.78
JESD-30 代码:S-PQCC-J84JESD-609代码:e0
长度:29.31 mm湿度敏感等级:3
功能数量:1端子数量:84
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC84,1.2SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):225
电源:5 V认证状态:Not Qualified
座面最大高度:4.57 mm子类别:Other Telecom ICs
最大压摆率:0.17 mA标称供电电压:5 V
表面贴装:YES技术:CMOS
电信集成电路类型:DIGITAL TIME SWITCH温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:29.31 mm
Base Number Matches:1

MT90820 数据手册

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CMOS ST-BUS FAMILY MT90820  
Large Digital Switch (LDX)  
Advance Information  
ISSUE 1  
May 1995  
Features  
2,048 channel non-blocking switch  
Maintains frame integrity on concatenated  
channels.  
Per-channel selection of minimum or constant  
throughput delay  
Ordering Information  
MT90820AP  
MT90820AL  
84 Pin PLCC  
100 Pin QFP  
Serial streams at 2.048, 4.096 or 8.192Mb/s  
Frame offset delay measurement  
Programmable frame delay offset  
Per-channel three-state control  
Per-channel message mode  
Control interface compatible to Intel/Motorola  
CPUs  
Block programming feature for connection  
memory  
-40 to +85°C  
Description  
The Large Digital Switch (LDX) is an advanced  
digital switch allowing the users to build up to 2048  
channel non-blocking switch. The serial interface can  
be at 2, 4 or 8 Mb/s compatible to ST-BUS/MVIP/  
HMVIP or GCI standards. The LDX can be  
programmed to provide either minimum or constant  
throughput delay on all its channels. The device also  
features three-state control and message mode on  
per-channel basis.  
ST-BUS/MVIP and GCI interfaces  
Test Port compatible to IEEE-1149.1 standard  
Applications  
Medium and large switching platforms  
C.O. switches  
CTI application  
Voice/data multiplexer  
Digital cross connects  
ST-BUS/HMVIP interface functions  
To manage the problem of line delays, each input  
stream can have an individually programmed input  
frame offset delay. The offset delay can be calibrated  
with a dedicated frame measurement facility inside  
the device.  
ODE  
VDD VSS  
TMS  
TDI TDO TCK TRSTB TEST RESETB  
Test Port  
STo0  
STo1  
STo2  
STo3  
STo4  
STo5  
STo6  
STo7  
STo8  
STo9  
STo10  
STo11  
STo12  
STo13  
STo14  
STo15  
STi0  
STi1  
STi2  
STi3  
STi4  
STi5  
STi6  
STi7  
STi8  
STi9  
STi10  
STi11  
STi12  
STi13  
STi14  
STi15  
Output  
MUX  
Serial  
to  
Multiple Buffer  
Data Memory  
Parallel  
to  
Parallel  
Converter  
Serial  
Converter  
Connection  
Memory  
Internal  
Registers  
Timing  
Unit  
Microprocessor Interface  
CLK FRM FE/ HMVIP AS/ IM DS  
CS R/W  
WR  
D15-D8/ CSTo  
AD7-AD0  
A7-A0 DTA  
ALE  
HCLK  
RD  
Figure 1 - Functional Block Diagram  
2-179  

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