Datasheet > MT90820

MT90820

更新时间： 2024-11-19 10:43:47

品牌	Logo	应用领域
MITEL		/
页数	文件大小	规格书
10页	73K
描述
CMOS ST-BUS? FAMILY Large Digital Switch (LDX)

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数据手册

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MT90820 数据手册

CMOS ST-BUS FAMILY MT90820

Large Digital Switch (LDX)

Advance Information

ISSUE 1

May 1995

Features

•

2,048 channel non-blocking switch

Maintains frame integrity on concatenated

channels.

Per-channel selection of minimum or constant

throughput delay

Ordering Information

MT90820AP

MT90820AL

84 Pin PLCC

100 Pin QFP

•

Serial streams at 2.048, 4.096 or 8.192Mb/s

Frame offset delay measurement

Programmable frame delay offset

Per-channel three-state control

Per-channel message mode

Control interface compatible to Intel/Motorola

CPUs

Block programming feature for connection

memory

-40 to +85°C

Description

The Large Digital Switch (LDX) is an advanced

digital switch allowing the users to build up to 2048

channel non-blocking switch. The serial interface can

be at 2, 4 or 8 Mb/s compatible to ST-BUS/MVIP/

HMVIP or GCI standards. The LDX can be

programmed to provide either minimum or constant

throughput delay on all its channels. The device also

features three-state control and message mode on

per-channel basis.

•

ST-BUS/MVIP and GCI interfaces

Test Port compatible to IEEE-1149.1 standard

Applications

•

Medium and large switching platforms

C.O. switches

CTI application

Voice/data multiplexer

Digital cross connects

ST-BUS/HMVIP interface functions

To manage the problem of line delays, each input

stream can have an individually programmed input

frame offset delay. The offset delay can be calibrated

with a dedicated frame measurement facility inside

the device.

ODE

V_DDV_SS

TMS

TDI TDO TCK TRSTB TEST RESETB

Test Port

STo0

STo1

STo2

STo3

STo4

STo5

STo6

STo7

STo8

STo9

STo10

STo11

STo12

STo13

STo14

STo15

STi0

STi1

STi2

STi3

STi4

STi5

STi6

STi7

STi8

STi9

STi10

STi11

STi12

STi13

STi14

STi15

Output

MUX

Serial

Multiple Buffer

Data Memory

Parallel

Converter

Serial

Converter

Connection

Memory

Internal

Registers

Timing

Unit

Microprocessor Interface

CLK FRM FE/ HMVIP AS/ IM DS

CS R/W

D15-D8/ CSTo

AD7-AD0

A7-A0 DTA

ALE

HCLK

Figure 1 - Functional Block Diagram

2-179

12 3 4 5 6 7...10

中文翻译

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与MT90820相关器件

型号	品牌	获取价格	描述	数据表
MT90820AL	MITEL	获取价格	CMOS ST-BUS? FAMILY Large Digital Switch (LDX)
MT90820AL	ZARLINK	获取价格	Large Digital Switch
MT90820AL1	ZARLINK	获取价格	Large Digital Switch
MT90820AP	ZARLINK	获取价格	Large Digital Switch
MT90820AP	MITEL	获取价格	CMOS ST-BUS? FAMILY Large Digital Switch (LDX)
MT90820AP1	ZARLINK	获取价格	Large Digital Switch
MT90820APR	ZARLINK	获取价格	Large Digital Switch
MT90820APR	MICROSEMI	获取价格	Telecom IC, CMOS, PQCC84
MT90820APR1	ZARLINK	获取价格	Large Digital Switch
MT90820APR1	MICROSEMI	获取价格	Telecom IC, CMOS, PQCC84