CMOS ST-BUSTM Family
MT90820
Large Digital Switch
Data Sheet
August 2005
Features
•
2,048 × 2,048 channel non-blocking switching at
Ordering Information
8.192 Mb/s
MT90820AP
84 Pin PLCC
Tubes
•
Per-channel variable or constant throughput
delay
Automatic identification of ST-BUS/GCI interfaces
MT90820AL
MT90820APR
MT90820AL1
MT90820AP1
100 Pin MQFP
84 Pin PLCC
Trays
Tape & Reel
100 Pin MQFP* Trays
•
•
84 Pin PLCC*
MT90820APR1 84 Pin PLCC*
*Pb Free Matte Tin
Tubes
Tape & Reel
Accept ST-BUS streams of 2.048 Mb/s,
4.096 Mb/s or 8.192 Mb/s
-40°C to +85°C
•
•
•
•
•
Automatic frame offset delay measurement
Per-stream frame delay offset programming
Per-channel high impedance output control
Per-channel message mode
Applications
•
•
•
•
•
•
Medium and large switching platforms
CTI application
Control interface compatible to Motorola non-
mulitplexed CPUs
Voice/data multiplexer
Digital cross connects
•
•
Connection memory block programming
IEEE-1149.1 (JTAG) Test Port
ST-BUS/GCI interface functions
Support IEEE 802.9a standard
V
V
SS
ODE
TMS
TDI TDO TCK TRST
IC
RESET
DD
Test Port
Loopback
STo0
STo1
STo2
STo3
STo4
STo5
STo6
STo7
STo8
STo9
STo10
STo11
STo12
STo13
STo14
STo15
STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
STi8
STi9
STi10
STi11
STi12
STi13
STi14
STi15
Serial
to
Parallel
to
Output
Parallel
Multiple Buffer
Data Memory
MUX
Serial
Converter
Converter
Connection
Memory
Internal
Registers
Timing
Unit
Microprocessor Interface
CLK F0i FE/ WFPS
HCLK
AS/ IM DS/
CS R/W
/WR
D15-D8/ CSTo
A7-A0 DTA
ALE
RD
AD7-AD0
Figure 1 - Functional Block Diagram
1
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