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MT90823AB PDF预览

MT90823AB

更新时间: 2024-11-19 10:43:47
品牌 Logo 应用领域
MITEL /
页数 文件大小 规格书
34页 152K
描述
3V Large Digital Switch

MT90823AB 数据手册

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MT90823  
3V Large Digital Switch  
DS5064  
ISSUE 3  
January 2000  
Features  
2,048 × 2,048 channel non-blocking switching  
at 8.192 Mb/s  
Ordering Information  
MT90823AP  
84 Pin PLCC  
100 Pin MQFP  
100 Pin LQFP  
120 Pin PBGA  
Per-channel variable or constant throughput  
delay  
MT90823AL  
MT90823AB  
MT90823AG  
Automatic identification of ST-BUS/GCI  
interfaces  
-40 to +85°C  
Accept ST-BUS streams of 2.048, 4.096 or  
8.192 Mb/s  
Description  
Automatic frame offset delay measurement  
Per-stream frame delay offset programming  
Per-channel high impedance output control  
Per-channel message mode  
The MT90823 Large Digital Switch has  
a
non-blocking switch capacity of: 2,048 x 2,048  
channels at a serial bit rate of 8.192 Mb/s; 1,024 x  
1,024 channels at 4.096 Mb/s; and 512 x 512  
channels at 2.048 Mb/s. The device has many  
features that are programmable on a per stream or  
per channel basis, including message mode, input  
offset delay and high impedance output control.  
Control interface compatible to Motorola  
non-multiplexed CPUs  
Connection memory block programming  
3.3V local I/O with 5V tolerant inputs and  
TTL-compatible outputs  
Per stream input delay control is particularly useful  
for managing large multi-chip switches that transport  
both voice channel and concatenated data channels.  
IEEE-1149.1 (JTAG) Test Port  
Applications  
Medium and large switching platforms  
In addition, the input stream can be individually  
calibrated for input frame offset using a dedicated  
pin.  
CTI application  
Voice/data multiplexer  
Digital cross connects  
ST-BUS/GCI interface functions  
Support IEEE 802.9a standard  
V
V
SS  
ODE  
TMS  
TDI TDO TCK TRST  
IC  
RESET  
DD  
Test Port  
Loopback  
STo0  
STo1  
STo2  
STo3  
STo4  
STo5  
STo6  
STo7  
STo8  
STo9  
STo10  
STo11  
STo12  
STo13  
STo14  
STo15  
STi0  
STi1  
STi2  
Serial  
to  
Parallel  
to  
STi3  
STi4  
Output  
MUX  
STi5  
Parallel  
Multiple Buffer  
Data Memory  
STi6  
Serial  
STi7  
Converter  
STi8  
Converter  
STi9  
STi10  
STi11  
STi12  
STi13  
STi14  
STi15  
Connection  
Memory  
Internal  
Registers  
Timing  
Unit  
Microprocessor Interface  
AS/ IM DS/  
CLK F0i FE/ WFPS  
HCLK  
CS R/W  
/WR  
D15-D8/ CSTo  
AD7-AD0  
A7-A0 DTA  
ALE  
RD  
Figure 1 - Functional Block Diagram  
1

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