Datasheet > MT90210

MT90210

更新时间： 2024-02-23 02:18:42

品牌	Logo	应用领域
MITEL		/
页数	文件大小	规格书
27页	136K
描述
Multi-Rate Parallel Access Circuit

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MT90210 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	QFP, QFP100,.7X1.0	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.22
Is Samacsys：	N	JESD-30 代码：	R-PQFP-G100
JESD-609代码：	e0	长度：	20 mm
功能数量：	1	端子数量：	100
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	QFP
封装等效代码：	QFP100,.7X1.0	封装形状：	RECTANGULAR
封装形式：	FLATPACK	峰值回流温度（摄氏度）：	260
电源：	5 V	认证状态：	Not Qualified
座面最大高度：	3.4 mm	子类别：	Other Telecom ICs
最大压摆率：	0.1 mA	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
电信集成电路类型：	TELECOM CIRCUIT	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	14 mm
Base Number Matches：	1

MT90210 数据手册

MT90210

Preliminary Information

how the data from the serial port is mapped into the

external dual port memory.

0000

1536 bytes

for TX

05FF

0800

BLOCK 0

BLOCK 1

0000

768 bytes

1536 bytes

for RX

for TX

02FF

0400

0DFF

1000

BLOCK 0

768 bytes

for RX

1536 bytes

for TX

06FF

0800

15FF

1800

768 bytes

1536 bytes

for RX

for TX

0AFF

0C00

1DFF

1FFF

BLOCK 1

768 bytes

for RX

MODES 2 & 3

24 bidirectional streams at 4.096Mb/s,

or 12 in / 12 out at 8.192Mb/s

0EFF

0FFF

MODE 1

24 bidirectional streams at 2.048Mb/s

Address outputs used: A0-A12

Address outputs used: A0-A11;

A12 always zero.

Legend:

unused memory space

Legend:

unused memory space

Figure 4 - Dual Port RAM Memory Map for

Modes 2 and 3

Figure 3 - Dual Port RAM Memory Map for

Mode 1

Mode 4: The MT90210 is conﬁgured such that the

24 serial streams are bidirectional and split into two

different functional groups: (i) streams S0-S15

operate at 2 Mb/s rate (512 timeslots), (ii) S16-S23

operate at 8.192 Mb/s rate (1024 timeslots). Memory

mapping for mode 4 is described in Figure 5. For

compatibility with legacy MVIP timing, mode 4

provides an additional clock input at 4.096 MHz

(HC4 input pin) which allows the device to detect

frame sync pulse (F0i) with a typical width of 244 ns.

In mode 4, the 16.384 (SCLK) and 4.096 (HC4) MHz

clocks should be in sync according to H-MVIP

speciﬁcations. The on-chip PLL doubles SCLK to

produce a CKout signal of 32.768 MHz. Figure 13

and Table 4 show the write and read operations on

the parallel port at the frame boundary.

Mode 2: When the device is conﬁgured for

4.096 Mb/s data rate operation, each of the 24 time-

division multiplexed serial streams is made up of 64

channels. In this data rate operation, the 24 serial

lines (S0-23) become bidirectional links at

4.096 Mb/s. Serial port clock (SCLK) is 8.192 MHz.

The on-chip PLL produces a phase locked 32.768

MHz clock (CKout) from the SCLK input. Figure 4

depicts how the data from the serial port is mapped

into the external dual port memory.

Mode 3: When the device is conﬁgured for 8.192

Mb/s data rate operation, each of the 24 time-

division multiplexed serial streams is made up of 128

channels. In this mode, bidirectional operation on the

serial port streams is not provided and the MT90210

is set in a 12 in / 12 out conﬁguration and the OEser

input is ignored. Streams S0-S11 are conﬁgured as

inputs, and S12-S23 are conﬁgured as outputs.

Serial port clock is 16.384 MHz. The on-chip PLL

doubles this clock to produce a CKout clock of

32.768 MHz. Figure 4 depicts how the data from the

serial port is mapped into the external dual port

memory. Figure 12 and Table 3 show the write and

read operations on the parallel port at the frame

boundary.

Mode 5: Identical operation as per mode 4 with the

difference that the 16.384 MHz clock is a differential

signal received at the two input pins, C16+ and C16-

of the MT90210 device. The differential clock is

needed to eliminate distortion in the clock signal

passing through a ribbon cable as per H-MVIP

speciﬁcation. The SCLK input is not used in this

mode. Memory mapping for mode 5 is depicted in

Figure 5.

2-150

1...3 4 567 8 9...27

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