MT90222/3/4
4/8/16 Port IMA/TC PHY Device
Data Sheet
March 2006
Features
IMA
Ordering Information
MT90222AG
MT90224AG
MT90223AG
MT90223AG2
MT90224AG2
384 Pin PBGA
384 Pin PBGA
384 Pin PBGA
384 Pin PBGA**
384 Pin PBGA**
Trays
Trays
Trays
Trays
Traus
•
Up to 16 T1, E1, J1, DSL links & up to 8 IMA
groups with 1 to 16 links/IMA group1
•
•
Supports symmetrical & asymmetrical operation
CTC (common transmit) & ITC (independent
transmit) clocking modes
**Pb Free Tin/Silver/Copper
-40°C to +85°C
•
•
Pre-processing of RX ICP (IMA control protocol)
cells
•
•
HEC (header error control) verification &
generation, error detection, filler cell filtering (IMA
mode) and idle/unassigned cell filtering (TC
mode)
IMA layer & per link statistics and alarms for
performance monitoring with MIB support
TC and UNI
TC layer statistics and error counts i.e. HEC
errors with MIB support
•
Supports mixed-mode operation: links not
assigned to an IMA group can be used in TC
mode
Standards Compliant
•
•
•
ATM Forum - IMA 1.1 (AF-PHY-0086.001) &
backwards compatible with IMA 1.0
•
ATM framing using cell delineation
ATM Forum - ATM over Fractional T1/E1 (AF-
PHY-0130.00)
1. MT90222 supports up to 4 serial links with maximum 4 groups
to be used - groups 0,1,2,3.
ITU G.804 cell mapping & ITU I.432 cell
delineation
MT90223 supports up to 8 serial links
MT90224 supports up to 16 serial links
RX External Static RAM
TDM Ring
Internal IMA
T1/E1/DSL
TDM
Ring
Control
Processors
(1 per group)
Rx Utopia
FIFo
RX
Utopia
Level 2
BUS
S/P
Utopia
I/F CTRL
T1/E1/DSL
Cell
Delineator
CD Circuits (1 per link)
TX
P/S
TDM
Ring
Tx Utopia
FIFo
Transmission
Convergence
Control
T1/E1/DSL
Serial TDM Ports
TC Circuits (1 per link)
(1 per link, up to 10Mb/s
per link)
Processor I/F
TDM Ring
Figure 1 - MT90222/3/4 Block Diagram (with Built-in IMA functions for up to 8 IMA Groups over
4/8/16 links)
1
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