Datasheet > MT90210

MT90210

更新时间： 2024-01-05 05:33:33

品牌	Logo	应用领域
MITEL		/
页数	文件大小	规格书
27页	136K
描述
Multi-Rate Parallel Access Circuit

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技术参数
数据手册

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MT90210 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	QFP, QFP100,.7X1.0	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.22
Is Samacsys：	N	JESD-30 代码：	R-PQFP-G100
JESD-609代码：	e0	长度：	20 mm
功能数量：	1	端子数量：	100
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	QFP
封装等效代码：	QFP100,.7X1.0	封装形状：	RECTANGULAR
封装形式：	FLATPACK	峰值回流温度（摄氏度）：	260
电源：	5 V	认证状态：	Not Qualified
座面最大高度：	3.4 mm	子类别：	Other Telecom ICs
最大压摆率：	0.1 mA	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
电信集成电路类型：	TELECOM CIRCUIT	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	14 mm
Base Number Matches：	1

MT90210 数据手册

MT90210

Preliminary Information

Pin Description (continued)

Name

Description

58-59,

61-62,

64,

P0-P1, Parallel Input/Output Data Bus. This 8 bit data bus is a bidirectional parallel port used to

P2-P3, perform 8-bit transactions between the MT90210 and the external dual port RAM. Data is

P4,

clocked in and out of the P0-P7 parallel port according to Figures 22 and 23.

66-68

P5-P7

Strobe

Strobe Output. This output is typically connected to the Chip-enable input of the external

dual port RAM. It is kept low during all read cycles, stays high during inactive periods and

goes low for the last half of a memory write cycle.

72-73,

75- 77,

80-82,

84-85,

87,

A0-A1, External Memory Address Outputs A0-A12. These 13 address output lines are provided

A2-A4,

A5-A7,

A8-A9,

A10,

by the MT90210 to allow a direct connection to an external dual port RAM.

89-90

A11-A12

RBC

Read Data Block Complete (output). A transition on this output is used to notify the

external CPU that the MT90210 has ﬁnished reading the contents of one entire 125µs

frame from the external dual port memory (e.g.; from addresses 0000h to 0FFFh in modes

3, 4 or 5). Whenever RBC toggles, the MT90210 starts reading the next half of the memory

(addresses 1000h to 1FFFh) while the local CPU updates the ﬁrst half with more data to

be sent. RBC toggles every 125µs. When this signal is low, the MT90210 is reading the

lower memory block.

WBC

Write Data Block Complete (Output). A transition on this output is used to notify the

external CPU that the MT90210 has ﬁnished writing the contents of one entire 125µs

frame into the external dual port memory (e.g; from addresses 0000h to 0FFFh in modes

3,4 or 5). Once WBC toggles, the local CPU can access the Dual port memory to get the

data while the MT90210 writes the contents of the next 125µs frame into the other half

(addresses 1000h to 1FFFh) of the dual port memory. WBC toggles every 125µs. When

this signal is low, the MT90210 is writing to the lower memory block.

4,16,

63, 71,

78, 86,

92, 99

Supply Input. +5V.

41, 55

Supply Input. +5V.

DD2

5,10,

17, 23,

60, 65,

69, 74,

79,83,

88, 93,

Ground.

SS2

2-148

1 2 345 6 7...27

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