Preliminary Information
MT90210
port RAM and connecting the ninth bit to OEser as
shown in Figure 9, the processor may disable an
individual channel by setting the ninth bit for that
channel in the transmit (TX) portion of the current
block. The remaining 8 bits for this channel may be
any value since they are ignored by the MT90210
when the ninth bit is 1. To avoid contention on the
serial bus, it is recommend that the user configure all
serial streams as inputs at start-up. This may be
done by setting all OEser bits to 1 in the TX portions
of both memory blocks. In mode 3, the serial streams
are permanently configured as 12 inputs and 12
outputs, and the state of OEser is ignored.
Functional Description
The MT90210 is a 100-pin device that converts
incoming serial telecom streams of 2.048, 4.096 or
8.192 Mb/s on to an 8-bit parallel bus, and converts
input data on this parallel bus to the outgoing serial
telecom links. The device is configured to perform
simultaneous parallel-to-serial and serial-to-parallel
conversion.
MT90210 interfaces up to 24 bidirectional serial data
streams to a byte oriented parallel port for access by
a dual-port RAM. It contains an address generator
for parallel port read and write operations directly to
an external dual port memory. A single MT90210
device can handle up to 3072 channels, 1536 on the
transmit and 1536 on the receive direction.
An Overview of CTI bus protocols
Multi-Vendor Integration Protocol (MVIP) provides a
coherent approach to building solutions for
worldwide markets by merging computing and
communications technologies under one open
architecture. MVIP ensures inter-operability among
Depending on the operation mode selected at the
mode pins (MD0-MD2), the 64 kb/s serial telecom
channels may be configured as inputs or outputs.
The data on the parallel bus is in a format suitable for
interfacing with popular dual port memories.
Depending on the data rate selected by the MD0-
MD2 input pins, serial data is clocked in and out on
the serial streams at either 2.048, 4.096 or 8.192
Mb/s, as shown in Figure 6. A mechanism for
implementing external double buffering is provided
by the Write Block Complete (WBC) and Read Block
Complete (RBC) output pins. Double buffering the
data allows the processor to independently access
an entire frame of data in the external memory while
the MT90210 reads or writes the complementary
frame in the memory. For example, in mode 3 (Figure
4), during the first frame the MT90210 will read and
write in to the first half of the memory space (Block
0) and during the second frame the MT90210 will
read and write in to the second half of the memory
space (Block 1). Within each block the transmit data
and receive data are separated and located at fixed
address locations. The operation of WBC and RBC is
shown in Figures 7a and 7b.
telephone-based
resources
(such
as
trunk
interfaces, voice, video, fax, text-to-speech, speech
recognition) for use within a computer chassis in an
individual or networked configuration. H-MVIP
addresses the need for higher telephony traffic
capacity in individual computer chassis. H-MVIP
defines three major items that together make a
useful digital telephony transport and switching
environment: the H-MVIP digital telephony bus with
up to 3072 "time-slots" of 64 Kb/s each; a bus
interface with digital switching that allows a group of
H-MVIP interfaced circuit boards to provide
complete, flexible, distributed telephony switching;
and a logical device driver model and standard
software interface to a logical model.
Operating Modes
The MT90210 device can operate in one of five
modes appropriate for different application needs.
Mode selection must be done while the device is in
reset (RST low and a valid clock applied to the PCLK
input). These modes are explained in the following
paragraphs.
On the external memory port side, the device
performs 8-bit wide operations with a cycle time of
30 or 61 ns. The parallel port operates at 16.384
MByte/s (for mode 1) or 32.768 MByte/s (for modes
2,3,4 and 5). To create the high speed clock required
to manage the byte operations at the parallel port, a
built in PLL multiplies the serial port input clock
(SCLK) by a factor of two or four depending on the
mode. In all operation modes, the user should
connect the PLL CKout to PCLK input.
Mode 1: The serial input/output format conforms to
the ST-BUS requirements when the data rate is
2.048 Mb/s (see Figure 6). Serial port clock (SCLK)
is 4.096 MHz. The on-chip PLL produces a phase
locked 16.384 MHz clock (CKout) from the SCLK
input. In this data rate operation, the 24 serial lines
(S0-23) become bidirectional links at 2.048 Mb/s.
The ST-BUS is a time-division multiplexed serial bus
with 32, 8-bit channels per frame. Frame boundaries
are delineated by the frame pulse. Figure 3 depicts
A separate input pin, Output Enable serial (OEser
pin 30), may be used to selectively tristate individual
64Kb/s serial links. By using a 9-bit external dual
2-149
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