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MT8967AS

更新时间： 2024-02-14 06:05:07
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 解码器编解码器PC
页数 文件大小 规格书
32页 609K
描述
Integrated PCM Filter Codec

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中文翻译

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MT8967AS 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：QCCN, LCC24,.4SQReach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.92
压伸定律：A-LAW滤波器：YES
最大增益公差：0.25 dBJESD-30 代码：S-PQCC-N24
JESD-609代码：e0线性编码：NOT AVAILABLE
负电源额定电压：-5 V功能数量：1
端子数量：24最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：QCCN封装等效代码：LCC24,.4SQ
封装形状：SQUARE封装形式：CHIP CARRIER
电源：+-5 V认证状态：Not Qualified
子类别：Codecs标称供电电压：5 V
表面贴装：YES技术：CMOS
电信集成电路类型：PCM CODEC温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：NO LEAD
端子节距：1.27 mm端子位置：QUAD
Base Number Matches：1

MT8967AS 数据手册

 浏览型号MT8967AS的Datasheet PDF文件第6页浏览型号MT8967AS的Datasheet PDF文件第7页浏览型号MT8967AS的Datasheet PDF文件第8页浏览型号MT8967AS的Datasheet PDF文件第10页浏览型号MT8967AS的Datasheet PDF文件第11页浏览型号MT8967AS的Datasheet PDF文件第12页 
MT8960/61/62/63/64/65/66/67  
Data Sheet  
TRANSMIT (A/D)  
BIT 2  
BIT 7  
BIT 1  
BIT 6  
BIT 0  
FILTER GAIN (dB)  
FUNCTION CONTROL  
0
0
1
1
0
1
0
1
Normal operation  
Digital Loopback  
Analog Loopback  
Powerdown  
Table 2 - Control States - Register A  
Control Registers A, B  
The contents of these registers control the filter/codec functions as described in Tables 2 and 3.  
Bit 7 of the registers is the MSB and is defined as the first bit of the serial data stream input (corresponding to the  
sign bit of the PCM word).  
On initial power-up these registers are set to the powerdown condition for a maximum of 25 clock cycles. During  
this time it is impossible to change the data in these registers.  
Chip Testing  
By enabling Register B with valid data (eight-bit control word input to CSTi when F1i=GNDD and CA= VCC) the chip  
testing mode can be entered. Bits 6 and 7 (most sign bits) define states for testing the transmit filter, receive filter  
and the codec function. The input in each case is VX input and the output in each case is VR output. (See Table 3 for  
details.)  
Loopback  
Loopback of the filter/codec is controlled by the control word entered into Register A. Bits 6 and 7 (most sign bits)  
provide either a digital or analog loopback condition. Digital loopback is defined as follows:  
•
PCM input data at DSTi is latched into the PCM input register and the output of this register is connected to  
the input of the 3-state PCM output register.  
•
•
The digital input to the PCM digital-to-analog decoder is disconnected, forced to zero (0).  
The output of the PCM encoder is disabled and thus the encoded data is lost. The PCM output at DSTo is  
determined by the PCM input data.  
Analog loopback is defined as follows:  
•
•
•
•
PCM input data is latched, decoded and filtered as normal but not output at VR.  
Analog output buffer at VR has its input shorted to GNDA and disconnected from the receive filter output.  
Analog input at VX is disconnected from the transmit filter input.  
The receive filter output is connected to the transmit filter input. Thus the decode signal is fed back through  
the receive path and encoded in the normal way. The analog output buffer at VR is not tested by this  
configuration.  
In both cases of loopback, DSTi is the input and DSTo is the output.  
9
Zarlink Semiconductor Inc.  
1...6789101112...32

中文翻译

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