ISO2-CMOS ST-BUS FAMILY MT8971B/72B
Digital Subscriber Interface Circuit
Digital Network Interface Circuit
ISSUE 7
May 1995
Features
•
Full duplex transmission over a single twisted
pair
Ordering Information
MT8971BE
22 Pin Plastic DIP
22 Pin Plastic DIP
22 Pin Ceramic DIP
28 Pin PLCC
•
•
•
•
•
•
•
•
Selectable 80 or 160 kbit/s line rate
Adaptive echo cancellation
MT8972BE
MT8972BC
MT8971BP
MT8972BP
Up to 3km (8971B) and 4 km (8972B)
ISDN compatible (2B+D) data format
Transparent modem capability
Frame synchronization and clock extraction
MITEL ST-BUS compatible
28 Pin PLCC
-40°C to +85°C
Description
The MT8971B (DSIC) and MT8972B (DNIC) are
multi-function devices capable of providing high
speed, full duplex digital transmission up to 160
kbit/s over a twisted wire pair. They use adaptive
echo-cancelling techniques and transfer data in
(2B+D) format compatible to the ISDN basic rate.
Several modes of operation allow an easy interface
to digital telecommunication networks including use
as a high speed limited distance modem with data
Low power (typically 50 mW), single 5V supply
Applications
•
Digital subscriber lines
rates up to 160 kbit/s.
Both devices function
•
High speed data transmission over twisted
wires
identically but with the DSIC having a shorter
maximum loop reach specification. The generic
"DNIC" will be used to reference both devices unless
otherwise noted.
•
•
Digital PABX line cards and telephone sets
80 or 160 kbit/s single chip modem
2
The MT8971B/72B is fabricated in Mitel’s ISO -
CMOS process.
DSTi/Di
LOUT
Differentially
Encoded Biphase
Transmitter
Transmit
Filter &
Line Driver
Transmit
Interface
Prescrambler
Scrambler
CDSTi/
CDi
LOUT
DIS
VBias
Transmit
Control
Address
Echo Canceller
Error
Signal
Timing
Register
F0/CLD
MUX
Master Clock
Phase Locked
Precan
C4/TCK
F0o/RCK
MS0
Echo Estimate
Transmit/
Clock
Receive
Timing &
Control
—
+
-1
Receive
Filter
DPLL
∑
MS1
+2
LIN
MS2
Sync Detect
Receive
RegC
Status
OSC2
OSC1
DSTo/Do
Differentially
Encoded Biphase
Receiver
De-
Prescrambler
Receive
Interface
Descrambler
CDSTo/
CDo
VDD
VSS VBias VRef
Figure 1 - Functional Block Diagram
9-107