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MT8967AS

更新时间： 2024-02-18 05:10:45
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 解码器编解码器PC
页数 文件大小 规格书
32页 609K
描述
Integrated PCM Filter Codec

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MT8967AS 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：QCCN, LCC24,.4SQReach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.92
压伸定律：A-LAW滤波器：YES
最大增益公差：0.25 dBJESD-30 代码：S-PQCC-N24
JESD-609代码：e0线性编码：NOT AVAILABLE
负电源额定电压：-5 V功能数量：1
端子数量：24最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：QCCN封装等效代码：LCC24,.4SQ
封装形状：SQUARE封装形式：CHIP CARRIER
电源：+-5 V认证状态：Not Qualified
子类别：Codecs标称供电电压：5 V
表面贴装：YES技术：CMOS
电信集成电路类型：PCM CODEC温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：NO LEAD
端子节距：1.27 mm端子位置：QUAD
Base Number Matches：1

MT8967AS 数据手册

 浏览型号MT8967AS的Datasheet PDF文件第3页浏览型号MT8967AS的Datasheet PDF文件第4页浏览型号MT8967AS的Datasheet PDF文件第5页浏览型号MT8967AS的Datasheet PDF文件第7页浏览型号MT8967AS的Datasheet PDF文件第8页浏览型号MT8967AS的Datasheet PDF文件第9页 
MT8960/61/62/63/64/65/66/67  
Data Sheet  
2C  
16.5 + S  
VRef  
X
V
[(128 )( 32 )]  
±
OFFSETC≠0  
where C = chord number (0-7)  
S = step number (0-15)  
VRef is a high impedance input with a varying capacitive load of up to 40 pF.  
The recommended reference voltage for the MT8960 series of codecs is 2.5 V ±0.5%. The output voltage from the  
reference source should have a maximum temperature coefficient of 100 ppm/C°. This voltage should have a total  
regulation tolerance of ±0.5% both for changes in the input voltage and output loading of the voltage reference  
source. A voltage reference circuit capable of meeting these specifications is shown in Figure 5. Analog  
Devices’AD1403A voltage reference circuit is capable of driving a large number of codecs due to the high input  
impedance of the VRef input. Normal precautions should be taken in PCB layout design to minimize noise coupling  
to this pin. A 0.1 µF capacitor connected from VRef to ground and located as close as possible to the codec is  
recommended to minimize noise entering through VRef. This capacitor should have good high frequency  
characteristics.  
NC  
8
NC  
7
NC  
6
NC  
5
V
Ref  
0.1 µF  
AD1403A  
MT8960-67  
FILTER/CODEC  
1
2
3
4
NC  
+5 V  
2.5 V  
Figure 5 - Typical Voltage Reference Circuit  
Timing  
The codec operates in a synchronous manner (see Figure 9a). The codec is activated on the first positive edge of  
C2i after F1i has gone low. The digital output at DSTo (which is a three-state output driver) will then change from  
a high impedance state to the sign bit of the encoded PCM word to be output. This will remain valid until the next  
positive edge, when the next most significant bit will be output.  
On the first negative clock edge (after F1i signal has been internally synchronized and CA is at GNDD or VEE) the  
logic signal present at DSTi will be clocked into the input shift register as the sign bit of the incoming PCM word.  
The eight-bit word is thus input at DSTi on negative edges of C2i and output at DSTo on positive edges of C2i.  
F1i must return to a high level after the eighth clock pulse causing DSTo to enter high impedance and  
preventing further input data to DSTi. F1i will continue to be sampled on every positive edge of C2i. (Note: F1i may  
subsequently be taken low during the same sampling frame to enable entry of serial data into CSTi. This occurs  
usually mid-frame, in conjunction with CA=VDD, in order to enter an 8-bit control word into Register B. In this case,  
PCM input and output are inhibited by CA at VDD.)  
Internally the codec will then perform a decode cycle on the newly input PCM word. The sampled and held analog  
signal thus decoded will be updated 25 µs from the start of the cycle. After this the analog input from the filter is  
sampled for 18 µs, after which digital conversion takes place during the remaining 82 µs of the sampling cycle.  
6
Zarlink Semiconductor Inc.  
1...3456789...32

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