Datasheet > MT8967AS

MT8967AS

更新时间： 2024-01-27 13:46:21

品牌	Logo	应用领域
加拿大卓联 - ZARLINK		解码器编解码器 PC
页数	文件大小	规格书
32页	609K
描述
Integrated PCM Filter Codec

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数据手册

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MT8967AS 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	QCCN, LCC24,.4SQ	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.92
压伸定律：	A-LAW	滤波器：	YES
最大增益公差：	0.25 dB	JESD-30 代码：	S-PQCC-N24
JESD-609代码：	e0	线性编码：	NOT AVAILABLE
负电源额定电压：	-5 V	功能数量：	1
端子数量：	24	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCN	封装等效代码：	LCC24,.4SQ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
电源：	+-5 V	认证状态：	Not Qualified
子类别：	Codecs	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
电信集成电路类型：	PCM CODEC	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	NO LEAD
端子节距：	1.27 mm	端子位置：	QUAD
Base Number Matches：	1

MT8967AS 数据手册

MT8960/61/62/63/64/65/66/67

Data Sheet

MT8961/63

MT8965/67

Digital Output

11111111

11110000

11100000

11010000

11000000

10110000

10100000

10101010

10100101

10110101

10000101

10010101

11100101

11110101

10010000

10000000

00000000

00010000

11000101

11010101

01010101

01000101

00100000

00110000

01000000

01010000

01100000

01110000

01111111

01110101

01100101

00010101

00000101

00110101

00100101

00101010

-2.5V

-1.25V

+2.5V

+1.25V

Analog Input Voltage (V

)

Bit 7...

MSB

LSB

Figure 4 - A-Law Encoder Transfer Characteristic

Functional Description

Figure 1 shows the functional block diagram of the MT8960-67. These devices provide the conversion interface

between the voiceband analog signals of a telephone subscriber loop and the digital signals required in a digital

PCM (pulse code modulation) switching system. Analog (voiceband) signals in the transmit path enter the chip at

V_X, are sampled at 8 kHz, and the samples quantized and assigned 8-bit digital values defined by logarithmic PCM

encoding laws. Analog signals in the receive path leave the chip at V_Rafter reconstruction from digital 8-bit words.

Separate switched capacitor filter sections are used for bandlimiting prior to digital encoding in the transmit path

and after digital decoding in the receive path. All filter clocks are derived from the 2.048 MHz master clock input,

C2i. Chip size is minimized by the use of common circuitry performing the A to D and D to A conversion. A

successive approximation technique is used with capacitor arrays to define the 16 steps and 8 chords in the signal

conversion process. Eight-bit PCM encoded digital data enters and leaves the chip serially on DSTi and DSTo

pins, respectively.

Transmit Path

Analog signals at the input (Vx) are firstly bandlimited to 508 kHz by an RC lowpass filter section. This performs the

necessary anti-aliasing for the following first-order sampled data lowpass pre-filter which is clocked at 512 kHz.

This further bandlimits the signal to 124 kHz before a fifth-order elliptic lowpass filter, clocked at 128 kHz, provides

the 3.4 kHz bandwidth required by the encoder section. A 50/60 Hz third-order highpass notch filter clocked at

8 kHz completes the transmit filter path. Accumulated DC offset is cancelled in this last section by a switched-

capacitor auto-zero loop which integrates the sign bit of the encoded PCM word, fed back from the codec and

Zarlink Semiconductor Inc.

1 2 345 6 7...32

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与MT8967AS相关器件

型号	品牌	描述	获取价格	数据表
MT8967AS1	ZARLINK	PCM Codec, A-Law, 1-Func, CMOS, PDSO20, 0.300 INCH, LEAD FREE, MS-013AC, SOIC-20	获取价格
MT8967AS1	MICROSEMI	PCM Codec, A-Law, 1-Func, CMOS, PDSO20, 0.300 INCH, LEAD FREE, MS-013AC, SOIC-20	获取价格
MT8967ASR	ZARLINK	PCM Codec, A-Law, 1-Func, CMOS, PDSO20, 0.300 INCH, MS-013AC, SOIC-20	获取价格
MT8967ASR	MICROSEMI	PCM Codec, A/MU-Law, 1-Func, CMOS, PDSO20,	获取价格
MT8967ASR1	MICROSEMI	PCM Codec, A/MU-Law, 1-Func, CMOS, PDSO20, LEAD FREE, SOIC-20	获取价格
MT8967AY	MICROSEMI	PCM Codec, A-Law, 1-Func, CMOS, PQCC24,	获取价格

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