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MT8967AS

更新时间： 2024-02-25 02:21:35
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 解码器编解码器PC
页数 文件大小 规格书
32页 609K
描述
Integrated PCM Filter Codec

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MT8967AS 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：QCCN, LCC24,.4SQReach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.92
压伸定律：A-LAW滤波器：YES
最大增益公差：0.25 dBJESD-30 代码：S-PQCC-N24
JESD-609代码：e0线性编码：NOT AVAILABLE
负电源额定电压：-5 V功能数量：1
端子数量：24最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：QCCN封装等效代码：LCC24,.4SQ
封装形状：SQUARE封装形式：CHIP CARRIER
电源：+-5 V认证状态：Not Qualified
子类别：Codecs标称供电电压：5 V
表面贴装：YES技术：CMOS
电信集成电路类型：PCM CODEC温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：NO LEAD
端子节距：1.27 mm端子位置：QUAD
Base Number Matches：1

MT8967AS 数据手册

 浏览型号MT8967AS的Datasheet PDF文件第4页浏览型号MT8967AS的Datasheet PDF文件第5页浏览型号MT8967AS的Datasheet PDF文件第6页浏览型号MT8967AS的Datasheet PDF文件第8页浏览型号MT8967AS的Datasheet PDF文件第9页浏览型号MT8967AS的Datasheet PDF文件第10页 
MT8960/61/62/63/64/65/66/67  
Data Sheet  
Since a single clock frequency of 2.048 MHz is required, all digital data is input and output at this rate. DSTo,  
therefore, assumes a high impedance state for all but 3.9 µs of the 125 µs frame. Similarly, DSTi input data is valid  
for only 3.9 µs.  
Digital Control Functions  
CSTi is a digital input (levels GNDD to VDD) which is used to control the function of the filter/codec. It operates in  
three different modes depending on the logic levels applied to the Control Address input (CA) and chip enable input  
(F1i) (see Table 1).  
Mode 1  
CA=-5V (VEE); CSTi=0V (GNDD)  
The filter/codec is in normal operation with nominal transmit and receive gain of 0dB. The SD outputs are in their  
active states and the test modes cannot be entered.  
CA = -5V (VEE); CSTi = +5V (VDD  
)
A state of powerdown is forced upon the chip whereby DSTo becomes high impedance, VR is connected to GNDA  
and all analog sections have power removed.  
Mode 2  
CA= -5V (VEE); CSTi receives an eight-bit control word  
CSTi accepts a serial data stream synchronously with DSTi (i.e., it accepts an eight-bit serial word in a 3.9 µs  
timeslot, updated every 125 µs, and is specified identically to DSTi for timing considerations). This eight-bit control  
word is entered into Control Register A and enables programming of the following functions: transmit and receive  
gain, powerdown, loopback. Register B is reset to zero and the SD outputs assume their inactive state. Test modes  
cannot be entered.  
Mode 3  
CA=0V (GNDD); CSTi receives an eight-bit control word  
As in Mode 2, the control word enters Register A and the aforementioned functions are controlled. In this mode,  
however, Register B is not reset, thus not affecting the states of the SD outputs.  
CA=+5V (VDD); CSTi receives an 8-bit control word  
In this case the control word is transferred into Register B. Register A is unaffected. The input and output of PCM  
data is inhibited.  
The contents of Register B controls the six uncommitted outputs SD0-SD5 (four outputs, SD0-SD3, on  
MT8960/61/64/65 versions of chip) and also provide entry into one of the three test modes of the chip.  
Note: For Modes 1 and 2, F1i must be at logic low for one period of 3.9 µs, in each 125 µs cycle, when PCM data  
is being input and output, and the control word at CSTi enters Register A. For Mode 3, F1i must be at a logic low for  
two periods of 3.9 µs, in each 125 µs cycle. In the first period, CA must be at GNDD or VEE, and in the second  
period CA must be high (VDD)  
.
7
Zarlink Semiconductor Inc.  
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