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MT8967AS PDF预览

MT8967AS

更新时间: 2024-01-09 03:42:37
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 解码器编解码器PC
页数 文件大小 规格书
32页 609K
描述
Integrated PCM Filter Codec

MT8967AS 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:QCCN, LCC24,.4SQReach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.92
压伸定律:A-LAW滤波器:YES
最大增益公差:0.25 dBJESD-30 代码:S-PQCC-N24
JESD-609代码:e0线性编码:NOT AVAILABLE
负电源额定电压:-5 V功能数量:1
端子数量:24最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:QCCN封装等效代码:LCC24,.4SQ
封装形状:SQUARE封装形式:CHIP CARRIER
电源:+-5 V认证状态:Not Qualified
子类别:Codecs标称供电电压:5 V
表面贴装:YES技术:CMOS
电信集成电路类型:PCM CODEC温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:NO LEAD
端子节距:1.27 mm端子位置:QUAD
Base Number Matches:1

MT8967AS 数据手册

 浏览型号MT8967AS的Datasheet PDF文件第7页浏览型号MT8967AS的Datasheet PDF文件第8页浏览型号MT8967AS的Datasheet PDF文件第9页浏览型号MT8967AS的Datasheet PDF文件第11页浏览型号MT8967AS的Datasheet PDF文件第12页浏览型号MT8967AS的Datasheet PDF文件第13页 
MT8960/61/62/63/64/65/66/67  
Data Sheet  
Logic Control Outputs SD0-5  
These outputs are directly controlled by the logic states of bits 0-5 in Register B. A logic low (GNDD) in Register B  
causes the SD outputs to assume an inactive state. A logic high (VDD) in Register B causes the SD outputs to  
assume an active state (see Table 3). SD0-2 switch between GNDD and VDD and may be used to control  
external logic or transistor circuitry, for example, that employed on the line card for performing such functions  
as relay drive for application of ringing to line, message waiting indication, etc.  
SD3-5 are used primarily to drive external analog circuitry. Examples may include the switching in or out of gain  
sections or filter sections (e.g., ring trip filter) (Figure 7).  
MT8962/63/66/67 provides all six SD outputs.  
MT8960/61/64/65 each packaged in an 18-pin DIP provide only four control outputs, SD0-3.  
Telephone Set  
2 Wire  
Analog  
PCM Highway  
Supervision  
Protection  
MT8960/61  
Battery  
Feed  
MT8962/63  
2W/4W  
Converter  
MT8964/65  
MT8966/67  
Ringing  
Figure 6 - Typical Line Termination  
LOGIC CONTROL OUTPUTS SD0-SD2  
BITS 0-2  
0
1
Inactive state - logic low (GNDD).  
Active state - logic high (VDD).  
BIT 3  
LOGIC CONTROL OUTPUT SD3  
0
1
Inactive state - High Impedance.  
Active state - GNDA.  
BITS 4,5  
LOGIC CONTROL OUTPUTS SD4, SD5  
0
1
Inactive state - High Impedance.  
Active state - GNDD.  
BIT 7 BIT 6  
CHIP TESTING CONTROLS  
0
0
Normal operation.  
10  
Zarlink Semiconductor Inc.  

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