Datasheet > MT8967AS

MT8967AS

更新时间： 2024-02-09 14:32:40

品牌	Logo	应用领域
加拿大卓联 - ZARLINK		解码器编解码器 PC
页数	文件大小	规格书
32页	609K
描述
Integrated PCM Filter Codec

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数据手册

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MT8967AS 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	QCCN, LCC24,.4SQ	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.92
压伸定律：	A-LAW	滤波器：	YES
最大增益公差：	0.25 dB	JESD-30 代码：	S-PQCC-N24
JESD-609代码：	e0	线性编码：	NOT AVAILABLE
负电源额定电压：	-5 V	功能数量：	1
端子数量：	24	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCN	封装等效代码：	LCC24,.4SQ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
电源：	+-5 V	认证状态：	Not Qualified
子类别：	Codecs	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
电信集成电路类型：	PCM CODEC	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	NO LEAD
端子节距：	1.27 mm	端子位置：	QUAD
Base Number Matches：	1

MT8967AS 数据手册

MT8960/61/62/63/64/65/66/67

Data Sheet

MT8962/63/66/67

MT8960/61/64/65

CSTi

DSTi

C2i

GNDD

VRef

GNDA

CSTi

DSTi

C2i

GNDD

VRef

GNDA

DSTo

VDD

SD5

SD4

F1i

DSTo

VDD

F1i

ANUL

VEE

SD0

SD1

SD2

VEE

SD0

SD3

SD2

SD1

SD3

18 PIN PDIP

20 PIN PDIP/SOIC

Figure 2 - Pin Connections

Pin Description

Pin Name

Description

CSTi

Control ST-BUS In is a TTL-compatible digital input used to control the function of the filter/codec.

Three modes of operation may be effected by applying to this input a logic high (V_DD), logic low

(GNDD), or an 8-bit serial word, depending on the logic states of CA and F1i.

Functions controlled are: powerdown, filter gain adjust, loopback, chip testing, SD outputs.

DSTi

C2i

Data ST-BUS In accepts the incoming 8-bit PCM word. Input is TTL-compatible.

Clock Input is a TTL-compatible 2.048 MHz clock.

DSTo Data ST-BUS Out is a three-state digital output driving the PCM bus with the outgoing 8-bit PCM

word.

V_DD

F1i

Positive power Supply (+5 V).

Synchronization Input is an active low digital input enabling (in conjunction with CA) the PCM input,

PCM output and digital control input. It is internally sampled on every positive edge of the clock, C2i,

and provides frame and channel synchronization.

Control Address is a three-level digital input which enables PCM input and output and determines

into which control register (A or B) the serial data, presented to CSTi, is stored.

SD3

System Drive Output is an open drain output of an N-channel transistor which has its source tied to

GNDA. Inactive state is open circuit.

SD4-5 System Drive Outputs are open drain outputs of N-channel transistors which have their source tied

to GNDD. Inactive state is open circuit.

SD0-2 System Drive Outputs are “Totempole“ CMOS outputs switching between GNDD and V_DD. Inactive

state is logic low.

V_EE

V_X

Negative power supply (-5 V).

Voice Transmit is the analog input to the transmit filter.

ANUL Auto Null is used to integrate an internal auto-null signal. A 0.1 µF capacitor must be connected

between this pin and GNDA.

V_R

Voice Receive is the analog output of the receive filter.

GNDA Analog ground (0 V).

V_Ref

Voltage Reference input to D to A converter.

GNDD Digital ground (0 V).

Zarlink Semiconductor Inc.

123 4 5 6 7...32

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与MT8967AS相关器件

型号	品牌	描述	获取价格	数据表
MT8967AS1	ZARLINK	PCM Codec, A-Law, 1-Func, CMOS, PDSO20, 0.300 INCH, LEAD FREE, MS-013AC, SOIC-20	获取价格
MT8967AS1	MICROSEMI	PCM Codec, A-Law, 1-Func, CMOS, PDSO20, 0.300 INCH, LEAD FREE, MS-013AC, SOIC-20	获取价格
MT8967ASR	ZARLINK	PCM Codec, A-Law, 1-Func, CMOS, PDSO20, 0.300 INCH, MS-013AC, SOIC-20	获取价格
MT8967ASR	MICROSEMI	PCM Codec, A/MU-Law, 1-Func, CMOS, PDSO20,	获取价格
MT8967ASR1	MICROSEMI	PCM Codec, A/MU-Law, 1-Func, CMOS, PDSO20, LEAD FREE, SOIC-20	获取价格
MT8967AY	MICROSEMI	PCM Codec, A-Law, 1-Func, CMOS, PQCC24,	获取价格

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