Datasheet > MT5C1005_05

MT5C1005_05

更新时间： 2024-11-08 05:50:35

品牌	Logo	应用领域
AUSTIN		存储静态存储器
页数	文件大小	规格书
13页	98K
描述
256K x 4 SRAM SRAM MEMORY ARRAY

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中文翻译

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数据手册

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MT5C1005_05 数据手册

SRAM

MT5C1005

Austin Semiconductor, Inc.

256K x 4 SRAM

SRAM MEMORY ARRAY

PIN ASSIGNMENT

(Top View)

32-Pin LCC (EC)

32-Pin SOJ (DCJ)

AVAILABLE AS MILITARY

SPECIFICATIONS

•MIL-STD-883

28-Pin DIP (C)

(400 MIL)

Vcc

DQ4

DQ3

DQ2

DQ1

WE\

A12

A10

A11

A13

A14

A15

A16

A17

A10

A11

A12

A13

A14

A15

A16 10

A17 11

CE\ 12

OE\ 13

Vss 14

FEATURES

• High Speed: 20, 25, 35, and 45

• Battery Backup: 2V data retention

• Low power standby

• High-performance, low-power CMOS double-metal

process

• Single +5V (+10%) Power Supply

• Easy memory expansion with CE\ and OE\ options.

• All inputs and outputs are TTL compatible

DQ4

DQ3

DQ2

DQ1

WE\

CE\

OE\

Vss

32-Pin Flat Pack (F)

32-Pin LCC (ECW)

Vcc

3 2

3 1

4 3 2 1 31 32 30

3 0

A12

A10

A11

A13

2 9

OPTIONS

• Timing

MARKING

2 8

2 9

2 8

2 7

2 6

2 5

2 4

2 3

2 2

2 1

A10

A11

A12

A13

A14

A15 1 0

A16 1 1

A17 1 2

CE\ 1 3

2 7

2 6

20ns access

25ns access

35ns access

45ns access

55ns access

70ns access

-20

2 5

A14

A15

A16

A17

2 4

DQ4

-25

-35

-45

-55*

-70*

1 0

1 1

1 2

1 3

1 4

1 5

1 6

2 3

2 2

2 1

2 0

1 9

1 8

1 7

DQ4

DQ3

DQ2

DQ1

WE\

CE\

OE\

Vss

14 15 16 17 18 19 20

• Package(s)

Ceramic DIP (400 mil)

No. 109

Ceramic Quad LCC (contact factory)ECW

No. 206

No. 207

No. 303

No. 501

GENERAL DESCRIPTION

Ceramic LCC

Ceramic Flatpack

Ceramic SOJ

The Austin Semiconductor SRAM family employs

high-speed, low power CMOS designs fabricated using double-

layer metal, double-layer polysilicon technology.

DCJ

For flexibility in high-speed memory applications, ASI

offers chip enable (CE\) and output enable (OE\) capability.

These enhancements can place the outputs in High-Z for addi-

tional flexibility in system design. Writing to these devices is

accomplished when write enable (WE\) and CE\ inputs are both

LOW. Reading is accomplished when WE\ remains HIGH while

CE\ and OE\ go LOW. The devices offer a reduced power

standby mode when disabled. This allows system designs to

achieve low standby power requirements.

• OperatingTemperature Ranges

Industrial (-40^oC to +85^oC)

Military (-55^oC to +125^oC)

• 2V data retention/low power

*Electrical characteristics identical to those provided for the

45ns access devices.

All devices operation from a single +5V power supply

and all inputs and outputs are fully TTL compatible.

For more products and information

please visit our web site at

www.austinsemiconductor.com

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

MT5C1005

Rev. 3.2 06/05

12 3 4 5 6 7...13

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与MT5C1005_05相关器件

型号	品牌	获取价格	描述	数据表
MT5C1005C-15L/883C	MICROSS	获取价格	Standard SRAM, 256KX4, 15ns, CMOS, CDIP28, 0.400 INCH, CERAMIC, DIP-28
MT5C1005C-20/883C	AUSTIN	获取价格	256K x 4 SRAM SRAM MEMORY ARRAY
MT5C1005C-20/IT	AUSTIN	获取价格	256K x 4 SRAM SRAM MEMORY ARRAY
MT5C1005C-20/IT	MICROSS	获取价格	Standard SRAM, 256KX4, 20ns, CMOS, CDIP28, 0.400 INCH, CERAMIC, DIP-28
MT5C1005C-20/XT	AUSTIN	获取价格	256K x 4 SRAM SRAM MEMORY ARRAY
MT5C1005C-20/XT	MICROSS	获取价格	Standard SRAM, 256KX4, 20ns, CMOS, CDIP28, 0.400 INCH, CERAMIC, DIP-28
MT5C1005C-20E/883C	MICROSS	获取价格	Standard SRAM, 256KX4, 20ns, CMOS, CDIP28, 0.400 INCH, CERAMIC, DIP-28
MT5C1005C-20L/883C	AUSTIN	获取价格	256K x 4 SRAM SRAM MEMORY ARRAY
MT5C1005C-20L/IT	AUSTIN	获取价格	256K x 4 SRAM SRAM MEMORY ARRAY
MT5C1005C-20L/XT	AUSTIN	获取价格	256K x 4 SRAM SRAM MEMORY ARRAY

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