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MT5C1005C-35/IT

更新时间： 2024-11-08 20:30:39
品牌 Logo 应用领域
MICROSS 静态存储器内存集成电路
页数 文件大小 规格书
13页 168K
描述
Standard SRAM, 256KX4, 35ns, CMOS, CDIP28, 0.400 INCH, CERAMIC, DIP-28

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MT5C1005C-35/IT 数据手册

 浏览型号MT5C1005C-35/IT的Datasheet PDF文件第2页浏览型号MT5C1005C-35/IT的Datasheet PDF文件第3页浏览型号MT5C1005C-35/IT的Datasheet PDF文件第4页浏览型号MT5C1005C-35/IT的Datasheet PDF文件第5页浏览型号MT5C1005C-35/IT的Datasheet PDF文件第6页浏览型号MT5C1005C-35/IT的Datasheet PDF文件第7页 
SRAM  
MT5C1005  
Austin Semiconductor, Inc.  
256K x 4 SRAM  
PIN ASSIGNMENT  
(Top View)  
SRAM MEMORY ARRAY  
32-Pin LCC (EC)  
32-Pin SOJ (DCJ)  
AVAILABLE AS MILITARY  
SPECIFICATIONS  
•MIL-STD-883  
28-Pin DIP (C)  
(400 MIL)  
A7  
A8  
A9  
1
2
3
4
5
6
7
8
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
Vcc  
A6  
A5  
A2  
A4  
A3  
A1  
NC  
NC  
A7  
A8  
A9  
1
2
3
4
5
6
7
8
9
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
Vcc  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
NC  
DQ4  
DQ3  
DQ2  
DQ1  
WE\  
A12  
A10  
A11  
A13  
NC  
A14  
A15  
A16  
A17  
NC  
A10  
A11  
A12  
A13  
A14  
A15  
A16 10  
A17 11  
CE\ 12  
OE\ 13  
Vss 14  
FEATURES  
• High Speed: 20, 25, 35, and 45  
• Battery Backup: 2V data retention  
• Low power standby  
9
10  
11  
12  
13  
14  
15  
16  
A0  
NC  
DQ4  
DQ3  
DQ2  
DQ1  
WE\  
• High-performance, low-power CMOS double-metal  
process  
• Single +5V (+10%) Power Supply  
• Easy memory expansion with CE\ and OE\ options.  
• All inputs and outputs are TTL compatible  
CE\  
OE\  
Vss  
32-Pin Flat Pack (F)  
32-Pin LCC (ECW)  
1
A7  
A8  
Vcc  
A6  
3 2  
2
3 1  
3
4 3 2 1 31 32 30  
A9  
A5  
3 0  
4
A12  
A10  
A11  
A13  
NC  
A2  
2 9  
OPTIONS  
• Timing  
MARKING  
5
A4  
2 8  
2 9  
2 8  
2 7  
2 6  
2 5  
2 4  
2 3  
2 2  
2 1  
A2  
A4  
A3  
A1  
A0  
NC  
NC  
NC  
DQ4  
A10  
A11  
A12  
A13  
A14  
A15 1 0  
A16 1 1  
A17 1 2  
CE\ 1 3  
5
6
7
8
9
6
A3  
2 7  
7
A1  
2 6  
20ns access  
25ns access  
35ns access  
45ns access  
55ns access  
70ns access  
-20  
8
NC  
NC  
A0  
2 5  
9
A14  
A15  
A16  
A17  
NC  
2 4  
-25  
-35  
-45  
-55*  
-70*  
1 0  
1 1  
1 2  
1 3  
1 4  
1 5  
1 6  
2 3  
2 2  
2 1  
2 0  
1 9  
1 8  
1 7  
NC  
DQ4  
DQ3  
DQ2  
DQ1  
WE\  
CE\  
OE\  
Vss  
14 15 16 17 18 19 20  
• Package(s)  
Ceramic DIP (400 mil)  
C
No. 109  
Ceramic Quad LCC (contact factory)ECW  
No. 206  
No. 207  
No. 303  
No. 501  
GENERAL DESCRIPTION  
Ceramic LCC  
Ceramic Flatpack  
Ceramic SOJ  
EC  
F
DCJ  
The Austin Semiconductor SRAM family employs  
high-speed, low power CMOS designs fabricated using double-  
layer metal, double-layer polysilicon technology.  
For flexibility in high-speed memory applications, ASI  
offers chip enable (CE\) and output enable (OE\) capability.  
These enhancements can place the outputs in High-Z for addi-  
tional flexibility in system design. Writing to these devices is  
accomplished when write enable (WE\) and CE\ inputs are both  
LOW. Reading is accomplished when WE\ remains HIGH while  
CE\ and OE\ go LOW. The devices offer a reduced power  
standby mode when disabled. This allows system designs to  
achieve low standby power requirements.  
• Operating Temperature Ranges  
Industrial (-40oC to +85oC)  
IT  
XT  
Military (-55oC to +125oC)  
• 2V data retention/low power  
L
*Electrical characteristics identical to those provided for the  
45ns access devices.  
All devices operation from a single +5V power supply  
and all inputs and outputs are fully TTL compatible.  
For more products and information  
please visit our web site at  
www.austinsemiconductor.com  
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
MT5C1005  
Rev. 3.1 1/01  
1
1234567...13

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MT5C1005C-35/XT AUSTIN

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MT5C1005C-35/XT MICROSS

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MT5C1005C-35L/IT AUSTIN

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MT5C1005C-35L/XT AUSTIN

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MT5C1005C-35LE/883C MICROSS

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 		Standard SRAM, 256KX4, 35ns, CMOS, CDIP28, 0.400 INCH, CERAMIC, DIP-28
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 		256K x 4 SRAM SRAM MEMORY ARRAY

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