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MT5C1005C-15L/883C PDF预览

MT5C1005C-15L/883C

更新时间： 2024-09-20 04:47:59
品牌 Logo 应用领域
MICROSS 静态存储器
页数 文件大小 规格书
8页 89K
描述
Standard SRAM, 256KX4, 15ns, CMOS, CDIP28, 0.400 INCH, CERAMIC, DIP-28

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MT5C1005C-15L/883C 数据手册

 浏览型号MT5C1005C-15L/883C的Datasheet PDF文件第2页浏览型号MT5C1005C-15L/883C的Datasheet PDF文件第3页浏览型号MT5C1005C-15L/883C的Datasheet PDF文件第4页浏览型号MT5C1005C-15L/883C的Datasheet PDF文件第5页浏览型号MT5C1005C-15L/883C的Datasheet PDF文件第6页浏览型号MT5C1005C-15L/883C的Datasheet PDF文件第7页 
MT5C1005 883C  
256K x 4 SRAM  
AUSTIN SEMICONDUCTOR, INC.  
SRAM  
256K x 4 SRAM  
AVAILABLE AS MILITARY  
SPECIFICATIONS  
PIN ASSIGNMENT (Top View)  
•
MIL-STD-883  
28-Pin DIP  
(400 MIL)  
32-Pin LCC  
32-Pin SOJ  
FEATURES  
•
•
•
•
High speed: 15, 20, 25, 35 and 45ns  
Battery Backup: 2V data retention  
Low power standby  
High-performance, low-power, CMOS double-metal  
process  
A7  
A8  
A9  
1
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
Vcc  
A6  
A5  
A2  
A4  
A7  
A8  
A9  
A10  
A11  
A12  
A13  
A14  
A15  
1
2
3
4
5
6
7
8
9
28 Vcc  
27 A6  
26 A5  
25 A4  
24 A3  
23 A2  
22 A1  
21 A0  
20 NC  
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
A12  
A10  
A11  
A13  
NC  
A14  
A15  
A16  
A17  
NC  
CE  
•
•
•
Single +5V (±10%) power supply  
Easy memory expansion with CE and OE options  
All inputs and outputs are TTL compatible  
A3  
A1  
NC  
NC  
A0  
NC  
DQ4  
DQ3  
DQ2  
DQ1  
WE  
OPTIONS  
MARKING  
A16 10 19 DQ4  
A17 11 18 DQ3  
CE 12 17 DQ2  
OE 13 16 DQ1  
Vss 14 15 WE  
•
Timing  
OE  
Vss  
15ns access (Contact factory)  
20ns access  
-15  
-20  
25ns access  
-25  
35ns access  
-35  
45ns access  
55ns access  
70ns access  
-45  
-55*  
-70*  
32-Pin LCC  
32-Pin Flat Pack  
•
Packages  
A7  
A8  
A9  
1
2
3
4
5
6
7
8
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
Vcc  
A6  
A5  
A2  
A4  
4
3 2 1 32 31 30  
Ceramic DIP (400 mil)  
Ceramic Flat Pack  
Ceramic LCC  
Ceramic SOJ  
Ceramic Quad LCC (Contact factory)  
C
F
No. 109  
No. 303  
5
6
7
8
9
29  
28  
27  
26  
25  
24  
23  
22  
21  
A2  
A
A10  
1  
A12  
A10  
A11  
A13  
NC  
A14  
A15  
A16  
A17  
NC  
CE  
A4  
A
A3  
A
A11  
2
A12  
3
A134  
A1  
A
A3  
A1  
A0  
N
A145  
10  
N156  
11  
NC  
N
EC No. 207  
DCJ No. 501  
ECW No. 206  
NC  
NC  
A0  
NC  
DQ4  
DQ3  
DQ2  
DQ1  
WE  
NC  
A
A167  
9
12  
NC  
N
A17  
10  
11  
12  
13  
14  
15  
16  
13  
DQ4  
CE  
14 1516 17 18 19 20  
OE  
Vss  
•
•
2V data retention, low power standby  
Radiation Tolerant (Epi)  
L
E
*Electrical characteristics identical to those provided for the 45ns  
access devices.  
GENERAL DESCRIPTION  
write enable ( WE) and CE inputs are both LOW. Reading  
is accomplished when WE remains HIGH while CE and  
OE go LOW. The devices offer a reduced power standby  
mode when disabled.This allows system designs to achieve  
low standby power requirements.  
The Austin Semiconductor SRAM family employs high-  
speed, low-power CMOS designs using a four transistor  
memory cell. Austin Semiconductor SRAMs are fabricated  
using double-layer metal, double-layer polysilicon tech-  
nology.  
The “L” version provides an approximate 50 percent  
reduction in CMOS standby current (ISBC2) over the stan-  
dard version.  
All devices operate from a single +5V power supply and  
all inputs and outputs are fully TTL compatible.  
For flexibility in high-speed memory applications, Aus-  
tin Semiconductor offers chip enable (CE) and output en-  
able (OE) capability. These enhancements can place the  
outputs in High-Z for additional flexibility in system  
design. Writing to these devices is accomplished when  
MT5C1005 883C  
REV. 11/97  
DS000005  
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.  
1-57  
12345678

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