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MT58L128V18FT-10 PDF预览

MT58L128V18FT-10

更新时间: 2024-09-17 03:11:39
品牌 Logo 应用领域
镁光 - MICRON 内存集成电路静态存储器
页数 文件大小 规格书
24页 481K
描述
2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM

MT58L128V18FT-10 技术参数

是否Rohs认证: 不符合生命周期:Transferred
零件包装代码:QFP包装说明:PLASTIC, TQFP-100
针数:100Reach Compliance Code:not_compliant
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.45Is Samacsys:N
最长访问时间:10 ns其他特性:FLOW-THROUGH ARCHITECTURE
最大时钟频率 (fCLK):66 MHzI/O 类型:COMMON
JESD-30 代码:R-PQFP-G100JESD-609代码:e0
长度:20 mm内存密度:2359296 bit
内存集成电路类型:CACHE SRAM内存宽度:18
功能数量:1端子数量:100
字数:131072 words字数代码:128000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:128KX18
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP100,.63X.87
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE
并行/串行:PARALLEL电源:2.5,3.3 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.01 A子类别:SRAMs
最大压摆率:0.15 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD宽度:14 mm
Base Number Matches:1

MT58L128V18FT-10 数据手册

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2Mb: 128K x 18, 64K x 32/36  
FLOW-THROUGH SYNCBURST SRAM  
2Mb SYNCBURST™  
SRAM  
MT58L128L18F, MT58L64L32F,  
MT58L64L36F; MT58L128V18F,  
MT58L64V32F, MT58L64V36F  
3.3V VDD, 3.3V or 2.5V I/O, Flow-Through  
FEATURES  
• Fast clock and OE# access times  
• Single +3.3V +0.3V/-0.165V power supply (VDD)  
• Separate +3.3V or +2.5V isolated output buffer  
supply (VDDQ)  
100-PinTQFP**  
• SNOOZE MODE for reduced-power standby  
• Common data inputs and data outputs  
• Individual BYTE WRITE control and GLOBAL  
WRITE  
• Three chip enables for simple depth expansion and  
address pipelining  
• Clock-controlled and registered addresses, data  
I/Os and control signals  
• Internally self-timed WRITE cycle  
• Burst control pin (interleaved or linear burst)  
• Automatic power-down  
**JEDEC-standard MS-026 BHA (LQFP).  
• 100-pin TQFP package  
• Low capacitive bus loading  
• x18, x32, and x36 versions available  
GENERALDESCRIPTION  
The Micron® SyncBurstSRAM family employs  
high-speed, low-power CMOS designs that are fabri-  
cated using an advanced CMOS process.  
OPTIONS  
MARKING  
• Timing (Access/Cycle/MHz)  
6.8ns/8.0ns/125 MHz  
7.5ns/8.8ns/113 MHz  
8.5ns/10ns/100 MHz  
10ns/15ns/66 MHz  
-6.8  
-7.5  
-8.5  
-10  
Micron’s 2Mb SyncBurst SRAMs integrate a 128K x  
18, 64K x 32, or 64K x 36 SRAM core with advanced  
synchronous peripheral circuitry and a 2-bit burst  
counter. All synchronous inputs pass through registers  
controlled by a positive-edge-triggered single clock  
input (CLK). The synchronous inputs include all ad-  
dresses, all data inputs, active LOW chip enable (CE#),  
two additional chip enables for easy depth expansion  
(CE2, CE2#), burst control inputs (ADSC#, ADSP#,  
ADV#), byte write enables (BWx#) and global write  
(GW#).  
Asynchronous inputs include the output enable  
(OE#), snooze enable (ZZ) and clock (CLK). There is also  
a burst mode pin (MODE) that selects between inter-  
leaved and linear burst modes. The data-out (Q), en-  
abled by OE#, is also asynchronous. WRITE cycles can  
be from one to two bytes wide (x18) or from one to four  
bytes wide (x32/x36), as controlled by the write control  
inputs.  
• Configurations  
3.3V I/O  
128K x 18  
64K x 32  
64K x 36  
MT58L128L18F  
MT58L64L32F  
MT58L64L36F  
2.5V I/O  
128K x 18  
64K x 32  
64K x 36  
MT58L128V18F  
MT58L64V32F  
MT58L64V36F  
• Packages  
100-pin TQFP  
T
• Operating Temperature Range  
Commercial (0°C to +70°C)  
None  
Part Number Example:  
MT58L64L36FT-8.5  
Burst operation can be initiated with either address  
status processor (ADSP#) or address status controller  
(ADSC#) input pins. Subsequent burst addresses can be  
internally generated as controlled by the burst advance  
pin (ADV#).  
2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM  
MT58L128L18F_2.p65 – Rev. 6/01  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
1
©2000,MicronTechnology,Inc.  

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