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MT40A1G8SA-062E AUT PDF预览

MT40A1G8SA-062E AUT

更新时间: 2024-11-22 14:58:59
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镁光 - MICRON 双倍数据速率
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21页 466K
描述
Adding ECC With DDR4 x16 Components

MT40A1G8SA-062E AUT 数据手册

 浏览型号MT40A1G8SA-062E AUT的Datasheet PDF文件第2页浏览型号MT40A1G8SA-062E AUT的Datasheet PDF文件第3页浏览型号MT40A1G8SA-062E AUT的Datasheet PDF文件第4页浏览型号MT40A1G8SA-062E AUT的Datasheet PDF文件第5页浏览型号MT40A1G8SA-062E AUT的Datasheet PDF文件第6页浏览型号MT40A1G8SA-062E AUT的Datasheet PDF文件第7页 
16Gb: x4, x8 TwinDie DDR4 SDRAM  
Description  
TwinDie1.2V DDR4 SDRAM  
MT40A4G4 – 128 Meg x 4 x 16 Banks x 2 Ranks  
MT40A2G8 – 64 Meg x 8 x 16 Banks x 2 Ranks  
Options  
Marking  
Description  
The 16Gb (TwinDie) DDR4 SDRAM uses  
• Configuration  
– 128 Meg x 4 x 16 banks x 2 ranks  
– 64 Meg x 8 x 16 banks x 2 ranks  
• FBGA package (Pb-free)  
– 78-ball FBGA  
(9.5mm x 13mm x 1.2mm) Die Rev :A  
– 78-ball FBGA  
4G4  
2G8  
Micron’s 8Gb DDR4 SDRAM die (essentially two ranks  
of the 8Gb DDR4 SDRAM). Refer to Micron’s 8Gb  
DDR4 SDRAM data sheet for the specifications not in-  
cluded in this document. Specifications for base part  
number MT40A2G4 correlate to TwinDie manufactur-  
ing part number MT40A4G4; specifications for base  
part number MT40A1G8 correlate to TwinDie manu-  
facturing part number MT40A2G8.  
FSE  
NRE  
(8.0mm x 12mm x 1.2mm) Die Rev :B  
• Timing – cycle time1  
– 0.750ns @ CL = 18 (DDR4-2666)  
– 0.833ns @ CL = 16 (DDR4-2400)  
– 0.833ns @ CL = 17 (DDR4-2400)  
– 0.937ns @ CL = 15 (DDR4-2133)  
– 0.937ns @ CL = 16 (DDR4-2133)  
• Self refresh  
-075E  
-083E  
-083  
-093E  
-093  
Features  
• Uses 8Gb Micron die  
Two ranks (includes dual CS#, ODT, and CKE balls)  
• Each rank has 4 groups of 4 internal banks for con-  
current operation  
• VDD = VDDQ = 1.2V (1.14–1.26V)  
• 1.2V VDDQ-terminated I/O  
• JEDEC-standard ball-out  
– Standard  
None  
• Operating temperature  
– Commercial (0°C TC 95°C)  
• Revision  
None  
:A  
:B  
• Low-profile package  
• TC of 0°C to 95°C  
– 0°C to 85°C: 8192 refresh cycles in 64ms  
– 85°C to 95°C: 8192 refresh cycles in 32ms  
1. CL = CAS (READ) latency.  
Note:  
Table 1: Key Timing Parameters  
Data Rate  
Speed Grade  
-075E1  
(MT/s)  
2666  
2400  
2400  
2133  
2133  
Target tRCD-tRP-CL  
tRCD (ns)  
13.5  
tRP (ns)  
13.5  
CL (ns)  
13.5  
18-18-18  
16-16-16  
17-17-17  
15-15-15  
16-16-16  
-083E2  
13.32  
14.16  
14.06  
15  
13.32  
14.16  
14.06  
15  
13.32  
14.16  
14.06  
15  
-0832  
-093E  
-093  
1. Backward compatible to 1600, CL = 11; 1866, CL = 13; 2133, CL = 15; and 2400, CL = 17.  
2. Backward compatible to 2133, CL = 15 (-093E).  
Notes:  
PDF: 09005aef85fd40a1  
DDR4_16Gb_x4_x8_2CS_TwinDie.pdf - Rev. D 12/16 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
1
© 2015 Micron Technology, Inc. All rights reserved.  
Products and specifications discussed herein are subject to change by Micron without notice.  

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