8Gb: x4, x8, x16 DDR4 SDRAM
Features
DDR4 SDRAM
MT40A2G4
MT40A1G8
MT40A512M16
Options1
Marking
Features
• VDD = VDDQ = 1.2V ±±60V
• VPP = 2.5V, –1250V, +2560V
• On-die, internal, adjustable VREFDQ generation
• 1.2V pseudo open-drain I/O
• Configuration
– 2 Gig x 4
– 1 Gig x 8
– 512 Meg x 1±
2G4
1G8
512M1±
• 78-ball FBGA package (Pb-free) – x4, x8
– 900 x 13.200 – Rev. A
– 800 x 1200 – Rev. B, D, G
– 7.500 x 1100 – Rev. E, H
• 9±-ball FBGA package (Pb-free) – x1±
– 900 x 1400 – Rev. A
– 800 x 1400 – Rev. B
– 7.500 x 13.500 – Rev. D, E, H
• Ti0ing – cycle ti0e
– 6.±25ns @ CL = 22 (DDR4-3266)
– 6.±82ns @ CL = 26 (DDR4-2933)
– 6.±82ns @ CL = 21 (DDR4-2933)
– 6.756ns @ CL = 18 (DDR4-2±±±)
– 6.756ns @ CL = 19 (DDR4-2±±±)
– 6.833ns @ CL = 1± (DDR4-2466)
– 6.833ns @ CL = 17 (DDR4-2466)
– 6.937ns @ CL = 15 (DDR4-2133)
– 6.937ns @ CL = 1± (DDR4-2133)
– 1.671ns @ CL = 13 (DDR4-18±±)
• Operating te0perature
• TC 0axi0u0 up to 95°C
PM
WE
SA
– ±40s, 8192-cycle refresh up to 85°C
– 320s, 8192-cycle refresh at >85°C to 95°C
• 1± internal banks (x4, x8): 4 groups of 4 banks each
• 8 internal banks (x1±): 2 groups of 4 banks each
• 8n-bit prefetch architecture
• Progra00able data strobe prea0bles
• Data strobe prea0ble training
• Co00and/Address latency (CAL)
• Multipurpose register READ and WRITE capability
• Write and read leveling
HA
JY
LY
-6±2E
-6±8E
-6±8
-675E
-675
-683E
-683
-693E
-693
• Self refresh 0ode
• Low-power auto self refresh (LPASR)
• Te0perature controlled refresh (TCR)
• Fine granularity refresh
• Self refresh abort
• Maxi0u0 power saving
• Output driver calibration
• No0inal, park, and dyna0ic on-die ter0ination
(ODT)
• Data bus inversion (DBI) for data bus
• Co00and/Address (CA) parity
• Databus write cyclic redundancy check (CRC)
• Per-DRAM addressability
-167E
– Co00ercial (6° ≤ TC ≤ 95°C)
– Industrial (–46° ≤ TC ≤ 95°C)
• Revision
None
IT
:A,
:B, :D, :G,
:E, :H
• Connectivity test (x1±)
• JEDEC JESD-79-4 co0pliant
• sPPR and hPPR capability
1. Not all options listed can be combined to
define an offered product. Use the part
catalog search on http://www.micron.com
for available offerings.
Note:
Table 1: Key Timing Parameters
Speed Grade
-062E6
Data Rate (MT/s)
Target tRCD-tRP-CL
tRCD (ns)
13.75
tRP (ns)
13.75
CL (ns)
13.75
13.64
14.32
3200
2933
2933
22-22-22
20-20-20
21-21-21
-068E5
-0685
13.64
13.64
14.32
14.32
09005aef861d1d4a
8gb_ddr4_dram.pdf - Rev. G 1/17 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
1
2015 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
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