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MSM54V12222B-20TA PDF预览

MSM54V12222B-20TA

更新时间: 2024-09-15 19:53:23
品牌 Logo 应用领域
冲电气 - OKI 光电二极管内存集成电路
页数 文件大小 规格书
16页 118K
描述
Memory Circuit, 256KX12, CMOS, PDSO44, 0.400 INCH, 0.8 MM PITCH, PLASTIC, TSOP2-44

MSM54V12222B-20TA 技术参数

生命周期:Transferred零件包装代码:TSOP2
包装说明:TSOP2,针数:44
Reach Compliance Code:unknownHTS代码:8542.32.00.71
风险等级:5.23JESD-30 代码:R-PDSO-G44
长度:18.41 mm内存密度:3145728 bit
内存集成电路类型:MEMORY CIRCUIT内存宽度:12
功能数量:1端子数量:44
字数:262144 words字数代码:256000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:256KX12
封装主体材料:PLASTIC/EPOXY封装代码:TSOP2
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.8 mm
端子位置:DUAL宽度:10.16 mm
Base Number Matches:1

MSM54V12222B-20TA 数据手册

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PEDS54V12222B-01  
1
Semiconductor  
MSM54V12222B  
This version: Sep. 2001  
Preliminary  
262,214-Word × 12-Bit Field Memory  
GENERAL DESCRIPTION  
The OKI MSM54V12222B is a high performance 3-Mbit, 256K × 12-bit, Field Memory. It is especially designed  
for high-speed serial access applications such as HDTVs, conventional NTSC TVs, VTRs, digital movies and  
Multi-media systems. MSM54V12222B is a FRAM for wide or low end use in general commodity TVs and VTRs  
exclusively. MSM54V12222B is not designed for the other use or high end use in medical systems, professional  
graphics systems which require long term picture storage, data storage systems and others. More than two  
MSM54V12222Bs can be cascaded directly without any delay devices among the MSM54V12222Bs. (Cascading  
of MSM54V12222B provides larger storage depth or a longer delay).  
Each of the 12-bit planes has separate serial write and read ports. These employ independent control clocks to  
support asynchronous read and write operations. Different clock rates are also supported that allow alternate data  
rates between write and read data streams.  
The MSM54V12222B provides high speed FIFO, First-In First-Out, operation without external refreshing:  
MSM54V12222B refreshes its DRAM storage cells automatically, so that it appears fully static to the users.  
Moreover, fully static type memory cells and decoders for serial access enable the refresh free serial access  
operation, so that serial read and/or write control clock can be halted high or low for any duration as long as the  
power is on. Internal conflicts of memory access and refreshing operations are prevented by special arbitration  
logic.  
The MSM54V12222B’s function is simple, and similar to a digital delay device whose delay-bit-length is easily  
set by reset timing. The delay length, number of read delay clocks between write and read, is determined by  
externally controlled write and read reset timings.  
Additional SRAM serial registers, or line buffers for the initial access of 256 × 12-bit enable high speed first-bit-  
access with no clock delay just after the write or read reset timings.  
Additionally, the MSM54V12222B has write mask function or input enable function (IE), and read-data skipping  
function or output enable function (OE) . The differences between write enable (WE) and input enable (IE), and  
between read enable (RE) and output enable (OE) are that WE and RE can stop serial write/read address  
increments, but IE and OE cannot stop the increment, when write/read clocking is continuously applied to  
MSM54V12222B. The input enable (IE) function allows the user to write into selected locations of the memory  
only, leaving the rest of the memory contents unchanged. This facilitates data processing to display a “picture in  
picture” on a TV screen.  
The MSM54V12222B is similar in operation and functionality to OKI 1-Mbit Field Memory MSM51V4222C and  
2-Mbit Field Memory MSM51V8222A. Three MSM51V4222Cs or one MSM51V4222C plus one  
MSM51V8222A can be replaced simply by one MSM54V12222B.  
1/16  

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