Datasheet > MPC9239EIR2

MPC9239EIR2

更新时间： 2024-11-04 14:53:55

品牌	Logo	应用领域
恩智浦 - NXP		时钟外围集成电路晶体
页数	文件大小	规格书
14页	353K
描述
900MHz, OTHER CLOCK GENERATOR, PQCC28, LEAD FREE, PLASTIC, LCC-28

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MPC9239EIR2 技术参数

是否Rohs认证：	符合	生命周期：	Transferred
零件包装代码：	QLCC	包装说明：	LEAD FREE, PLASTIC, LCC-28
针数：	28	Reach Compliance Code：	unknown
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.22	JESD-30 代码：	S-PQCC-J28
JESD-609代码：	e3	长度：	11.5062 mm
湿度敏感等级：	1	端子数量：	28
最高工作温度：	70 °C	最低工作温度：
最大输出时钟频率：	900 MHz	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装等效代码：	LDCC28,.5SQ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
峰值回流温度（摄氏度）：	260	电源：	3.3 V
主时钟/晶体标称频率：	20 MHz	认证状态：	Not Qualified
座面最大高度：	4.57 mm	子类别：	Clock Generators
最大压摆率：	100 mA	最大供电电压：	3.465 V
最小供电电压：	3.135 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Matte Tin (Sn)
端子形式：	J BEND	端子节距：	1.27 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	40
宽度：	11.5062 mm	uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, OTHER
Base Number Matches：	1

MPC9239EIR2 数据手册

MPC9239

Rev. 3, 08/2005

Freescale Semiconductor

Technical Data

900 MHz Low Voltage LVPECL

Clock Synthesizer

MPC9239

The MPC9239 is a 3.3 V compatible, PLL based clock synthesizer targeted for

high performance clock generation in mid-range to high-performance telecom,

networking, and computing applications. With output frequencies from

3.125 MHz to 900 MHz and the support of differential LVPECL output signals the

device meets the needs of the most demanding clock applications.

900 MHz LOW VOLTAGE

CLOCK SYNTHESIZER

Features

•

3.125 MHz to 900 MHz synthesized clock output signal

Differential LVPECL output

LVCMOS compatible control inputs

On-chip crystal oscillator for reference frequency generation

Alternative LVCMOS compatible reference input

3.3 V power supply

FN SUFFIX

28-LEAD PLCC PACKAGE

CASE 776-02

EI SUFFIX

28-LEAD PLCC PACKAGE

Pb-FREE PACKAGE

CASE 776-02

Fully integrated PLL

Minimal frequency overshoot

Serial 3-wire programming interface

Parallel programming interface for power-up

28 PLCC and 32 LQFP packaging

28-lead and 32-lead Pb-free package available

SiGe Technology

FA SUFFIX

32-LEAD LQFP PACKAGE

CASE 873A-04

Ambient temperature range 0°C to + 70°C

Pin and function compatible to the MC12439

AC SUFFIX

32-LEAD LQFP PACKAGE

Pb-FREE PACKAGE

CASE 873A-04

Functional Description

The internal crystal oscillator uses the external quartz crystal as the basis of

its frequency reference. The frequency of the internal crystal oscillator or external

reference clock signal is multiplied by the PLL. The VCO within the PLL operates over a range of 800 to 1800 MHz. Its output is

scaled by a divider that is configured by either the serial or parallel interfaces. The crystal oscillator frequency f_XTAL, the PLL

feedback-divider M and the PLL post-divider N determine the output frequency.

The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be M times the reference frequency

by adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve phase

lock. The PLL will be stable if the VCO frequency is within the specified VCO frequency range (800 to 1800 MHz). The M-value

must be programmed by the serial or parallel interface.

The PLL post-divider N is configured through either the serial or the parallel interfaces, and can provide one of four division

ratios (1, 2, 4, or 8). This divider extends performance of the part while providing a 50% duty cycle. The output driver is driven

differentially from the output divider, and is capable of driving a pair of transmission lines terminated 50 Ω to V_CC– 2.0 V. The

positive supply voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize

noise induced jitter.

The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[6:0] and N[1:0]

inputs to configure the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes

valid. On the LOW-to-HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the

serial interface. Internal pullup resistors are provided on the M[6:0] and N[1:0] inputs prevent the LVCMOS compatible control

inputs from floating. The serial interface centers on a twelve bit shift register. The shift register shifts once per rising edge of the

S_CLOCK input. The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this

document. The configuration latches will capture the value of the shift register on the HIGH-to-LOW edge of the S_LOAD input.

Refer to the programming section for more information. The TEST output reflects various internal node values, and is controlled

by the T[2:0] bits in the serial data stream. In order to minimize the PLL jitter, it is recommended to avoid active signal on the

TEST output. The PWR_DOWN pin, when asserted, will synchronously divide the f_OUTby 16. The power down sequence is

clocked by the PLL reference clock, thereby causing the frequency reduction to happen relatively slowly. Upon de-assertion of

the PWR_DOWN pin, the f_OUTinput will step back up to its programmed frequency in four discrete increments.

12 3 4 5 6 7...14

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与MPC9239EIR2相关器件

型号	品牌	获取价格	描述	数据表
MPC9239FA	MOTOROLA	获取价格	Clock Generator, 900MHz, CMOS, PQFP32, LQFP-32
MPC9239FA	FREESCALE	获取价格	900 MHz Low Voltage LVPECL Clock Synthesizer
MPC9239FA	NXP	获取价格	900MHz, OTHER CLOCK GENERATOR, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, MS-026BBA,
MPC9239FN	NXP	获取价格	IC,MISCELLANEOUS CLOCK GENERATOR,LDCC,28PIN,PLASTIC
MPC9239FN	MOTOROLA	获取价格	Clock Generator, 900MHz, CMOS, PQCC28, PLASTIC, LCC-28
MPC9239FN	FREESCALE	获取价格	900 MHz Low Voltage LVPECL Clock Synthesizer
MPC92429	MOTOROLA	获取价格	400 MHz Low Voltage PECL Clock Synthesizer
MPC92429AC	IDT	获取价格	Clock Generator, 400MHz, PQFP32, LEAD FREE, LQFP-32
MPC92429ACR2	NXP	获取价格	400MHz, OTHER CLOCK GENERATOR, PQFP32, LEAD FREE, LQFP-32
MPC92429EIR2	NXP	获取价格	400MHz, OTHER CLOCK GENERATOR, PQCC28, LEAD FREE, PLASTIC, LCC-28

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